Lines Matching +full:0 +full:x12000000
52 #size-cells = <0>;
89 reg = <0x100>;
96 reg = <0x101>;
103 reg = <0x102>;
110 reg = <0x103>;
117 reg = <0x200>;
124 reg = <0x201>;
128 cpu6: cpu@0 {
131 reg = <0x0>;
138 reg = <0x1>;
146 cpu_suspend = <0xc4000001>;
147 cpu_off = <0x84000002>;
148 cpu_on = <0xc4000003>;
163 #clock-cells = <0>;
168 soc: soc@0 {
172 ranges = <0x0 0x0 0x0 0x20000000>;
176 reg = <0x10000000 0x24>;
182 #address-cells = <0>;
184 reg = <0x12301000 0x1000>,
185 <0x12302000 0x2000>,
186 <0x12304000 0x2000>,
187 <0x12306000 0x2000>;
194 reg = <0x10010000 0x8000>;
221 reg = <0x12000000 0x8000>;
236 reg = <0x12060000 0x8000>;
245 reg = <0x13400000 0x8000>;
264 reg = <0x11cb0000 0x1000>;
275 reg = <0x13430000 0x1000>;
281 reg = <0x139b0000 0x1000>;
287 reg = <0x148f0000 0x1000>;
293 reg = <0x11c80000 0x10000>;
298 reg = <0x13500000 0x2000>;
301 #size-cells = <0>;
305 fifo-depth = <0x40>;
311 reg = <0x13800000 0x100>;
314 pinctrl-0 = <&uart0_bus>;
324 reg = <0x13810000 0x100>;
327 pinctrl-0 = <&uart1_bus>;
337 reg = <0x13820000 0x100>;
340 pinctrl-0 = <&uart2_bus>;
350 reg = <0x13830000 0x100>;
353 #size-cells = <0>;
355 pinctrl-0 = <&i2c0_bus>;
363 reg = <0x13840000 0x100>;
366 #size-cells = <0>;
368 pinctrl-0 = <&i2c1_bus>;
376 reg = <0x13850000 0x100>;
379 #size-cells = <0>;
381 pinctrl-0 = <&i2c2_bus>;
389 reg = <0x13860000 0x100>;
392 #size-cells = <0>;
394 pinctrl-0 = <&i2c3_bus>;
402 reg = <0x13870000 0x100>;
405 #size-cells = <0>;
407 pinctrl-0 = <&i2c4_bus>;
415 reg = <0x13880000 0x100>;
418 #size-cells = <0>;
420 pinctrl-0 = <&i2c5_bus>;
428 reg = <0x13890000 0x100>;
431 #size-cells = <0>;
433 pinctrl-0 = <&i2c6_bus>;
441 reg = <0x11cd0000 0x100>;
444 #size-cells = <0>;
446 pinctrl-0 = <&i2c7_bus>;