Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
44 clock-output-names = "fin_pll";
45 #clock-cells = <0>;
49 #address-cells = <1>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a57";
56 enable-method = "psci";
57 i-cache-size = <0xc000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <256>;
63 next-level-cache = <&atlas_l2>;
68 compatible = "arm,cortex-a57";
70 enable-method = "psci";
71 i-cache-size = <0xc000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <256>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <256>;
77 next-level-cache = <&atlas_l2>;
82 compatible = "arm,cortex-a57";
84 enable-method = "psci";
85 i-cache-size = <0xc000>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <256>;
88 d-cache-size = <0x8000>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <256>;
91 next-level-cache = <&atlas_l2>;
96 compatible = "arm,cortex-a57";
98 enable-method = "psci";
99 i-cache-size = <0xc000>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <256>;
102 d-cache-size = <0x8000>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <256>;
105 next-level-cache = <&atlas_l2>;
108 atlas_l2: l2-cache0 {
110 cache-size = <0x200000>;
111 cache-line-size = <64>;
112 cache-sets = <2048>;
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
130 compatible = "samsung,exynos4210-chipid";
134 gic: interrupt-controller@11001000 {
135 compatible = "arm,gic-400";
136 #interrupt-cells = <3>;
137 #address-cells = <0>;
138 interrupt-controller;
145 pdma0: dma-controller@10e10000 {
150 clock-names = "apb_pclk";
151 #dma-cells = <1>;
154 pdma1: dma-controller@10eb0000 {
159 clock-names = "apb_pclk";
160 #dma-cells = <1>;
163 clock_topc: clock-controller@10570000 {
164 compatible = "samsung,exynos7-clock-topc";
166 #clock-cells = <1>;
169 clock_top0: clock-controller@105d0000 {
170 compatible = "samsung,exynos7-clock-top0";
172 #clock-cells = <1>;
178 clock-names = "fin_pll", "dout_sclk_bus0_pll",
183 clock_top1: clock-controller@105e0000 {
184 compatible = "samsung,exynos7-clock-top1";
186 #clock-cells = <1>;
191 clock-names = "fin_pll", "dout_sclk_bus0_pll",
196 clock_ccore: clock-controller@105b0000 {
197 compatible = "samsung,exynos7-clock-ccore";
199 #clock-cells = <1>;
201 clock-names = "fin_pll", "dout_aclk_ccore_133";
204 clock_peric0: clock-controller@13610000 {
205 compatible = "samsung,exynos7-clock-peric0";
207 #clock-cells = <1>;
210 clock-names = "fin_pll", "dout_aclk_peric0_66",
214 clock_peric1: clock-controller@14c80000 {
215 compatible = "samsung,exynos7-clock-peric1";
217 #clock-cells = <1>;
231 clock-names = "fin_pll",
246 clock_peris: clock-controller@10040000 {
247 compatible = "samsung,exynos7-clock-peris";
249 #clock-cells = <1>;
251 clock-names = "fin_pll", "dout_aclk_peris_66";
254 clock_fsys0: clock-controller@10e90000 {
255 compatible = "samsung,exynos7-clock-fsys0";
257 #clock-cells = <1>;
260 clock-names = "fin_pll", "dout_aclk_fsys0_200",
264 clock_fsys1: clock-controller@156e0000 {
265 compatible = "samsung,exynos7-clock-fsys1";
267 #clock-cells = <1>;
274 clock-names = "fin_pll", "dout_aclk_fsys1_200",
281 compatible = "samsung,exynos4210-uart";
286 clock-names = "uart", "clk_uart_baud0";
291 compatible = "samsung,exynos4210-uart";
296 clock-names = "uart", "clk_uart_baud0";
301 compatible = "samsung,exynos4210-uart";
306 clock-names = "uart", "clk_uart_baud0";
311 compatible = "samsung,exynos4210-uart";
316 clock-names = "uart", "clk_uart_baud0";
321 compatible = "samsung,exynos7-pinctrl";
324 wakeup-interrupt-controller {
325 compatible = "samsung,exynos7-wakeup-eint";
326 interrupt-parent = <&gic>;
332 compatible = "samsung,exynos7-pinctrl";
338 compatible = "samsung,exynos7-pinctrl";
344 compatible = "samsung,exynos7-pinctrl";
350 compatible = "samsung,exynos7-pinctrl";
356 compatible = "samsung,exynos7-pinctrl";
362 compatible = "samsung,exynos7-pinctrl";
368 compatible = "samsung,exynos7-pinctrl";
374 compatible = "samsung,exynos7-pinctrl";
380 compatible = "samsung,exynos7-hsi2c";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&hs_i2c0_bus>;
388 clock-names = "hsi2c";
393 compatible = "samsung,exynos7-hsi2c";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&hs_i2c1_bus>;
401 clock-names = "hsi2c";
406 compatible = "samsung,exynos7-hsi2c";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&hs_i2c2_bus>;
414 clock-names = "hsi2c";
419 compatible = "samsung,exynos7-hsi2c";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&hs_i2c3_bus>;
427 clock-names = "hsi2c";
432 compatible = "samsung,exynos7-hsi2c";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&hs_i2c4_bus>;
440 clock-names = "hsi2c";
445 compatible = "samsung,exynos7-hsi2c";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&hs_i2c5_bus>;
453 clock-names = "hsi2c";
458 compatible = "samsung,exynos7-hsi2c";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&hs_i2c6_bus>;
466 clock-names = "hsi2c";
471 compatible = "samsung,exynos7-hsi2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&hs_i2c7_bus>;
479 clock-names = "hsi2c";
484 compatible = "samsung,exynos7-hsi2c";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&hs_i2c8_bus>;
492 clock-names = "hsi2c";
497 compatible = "samsung,exynos7-hsi2c";
500 #address-cells = <1>;
501 #size-cells = <0>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&hs_i2c9_bus>;
505 clock-names = "hsi2c";
510 compatible = "samsung,exynos7-hsi2c";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&hs_i2c10_bus>;
518 clock-names = "hsi2c";
523 compatible = "samsung,exynos7-hsi2c";
526 #address-cells = <1>;
527 #size-cells = <0>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&hs_i2c11_bus>;
531 clock-names = "hsi2c";
535 pmu_system_controller: system-controller@105c0000 {
536 compatible = "samsung,exynos7-pmu", "syscon";
541 compatible = "samsung,s3c6410-rtc";
546 clock-names = "rtc";
551 compatible = "samsung,exynos7-wdt";
555 clock-names = "watchdog";
556 samsung,syscon-phandle = <&pmu_system_controller>;
561 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
566 interrupt-names = "job", "mmu", "gpu";
572 compatible = "samsung,exynos7-dw-mshc-smu";
574 #address-cells = <1>;
575 #size-cells = <0>;
579 clock-names = "biu", "ciu";
580 fifo-depth = <0x40>;
585 compatible = "samsung,exynos7-dw-mshc";
587 #address-cells = <1>;
588 #size-cells = <0>;
592 clock-names = "biu", "ciu";
593 fifo-depth = <0x40>;
598 compatible = "samsung,exynos7-dw-mshc-smu";
600 #address-cells = <1>;
601 #size-cells = <0>;
605 clock-names = "biu", "ciu";
606 fifo-depth = <0x40>;
611 compatible = "samsung,exynos7-adc";
615 clock-names = "adc";
616 #io-channel-cells = <1>;
621 compatible = "samsung,exynos4210-pwm";
628 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
629 #pwm-cells = <3>;
631 clock-names = "timers";
635 compatible = "samsung,exynos7-tmu";
640 clock-names = "tmu_apbif", "tmu_sclk";
641 #thermal-sensor-cells = <0>;
645 compatible = "samsung,exynos7-ufs";
650 reg-names = "hci", "vs_hci", "unipro", "ufsp";
654 clock-names = "core_clk", "sclk_unipro_main";
655 freq-table-hz = <0 0>, <0 0>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
659 phy-names = "ufs-phy";
663 ufs_phy: ufs-phy@15571800 {
664 compatible = "samsung,exynos7-ufs-phy";
666 reg-names = "phy-pma";
667 samsung,pmu-syscon = <&pmu_system_controller>;
668 #phy-cells = <0>;
673 clock-names = "ref_clk", "rx1_symbol_clk",
678 usbdrd_phy: phy@15500000 {
679 compatible = "samsung,exynos7-usbdrd-phy";
686 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
687 samsung,pmu-syscon = <&pmu_system_controller>;
688 #phy-cells = <1>;
692 compatible = "samsung,exynos7-dwusb3";
696 clock-names = "usbdrd30", "usbdrd30_susp_clk",
698 #address-cells = <1>;
699 #size-cells = <1>;
707 phy-names = "usb2-phy", "usb3-phy";
712 thermal-zones {
713 atlas_thermal: cluster0-thermal {
714 polling-delay-passive = <0>; /* milliseconds */
715 polling-delay = <0>; /* milliseconds */
716 thermal-sensors = <&tmuctrl_0>;
717 #include "exynos7-trip-points.dtsi"
722 compatible = "arm,armv8-timer";
734 #include "exynos7-pinctrl.dtsi"
735 #include "arm/exynos-syscon-restart.dtsi"