Lines Matching +full:opp +full:- +full:600000000
1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
36 compatible = "arm,cortex-a57-pmu";
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
46 compatible = "fixed-clock";
47 clock-output-names = "oscclk";
48 #clock-cells = <0>;
52 #address-cells = <1>;
53 #size-cells = <0>;
55 cpu-map {
89 compatible = "arm,cortex-a53";
90 enable-method = "psci";
92 clock-frequency = <1300000000>;
94 clock-names = "apolloclk";
95 operating-points-v2 = <&cluster_a53_opp_table>;
96 #cooling-cells = <2>;
97 i-cache-size = <0x8000>;
98 i-cache-line-size = <64>;
99 i-cache-sets = <256>;
100 d-cache-size = <0x8000>;
101 d-cache-line-size = <64>;
102 d-cache-sets = <128>;
103 next-level-cache = <&cluster_a53_l2>;
108 compatible = "arm,cortex-a53";
109 enable-method = "psci";
111 clock-frequency = <1300000000>;
112 operating-points-v2 = <&cluster_a53_opp_table>;
113 #cooling-cells = <2>;
114 i-cache-size = <0x8000>;
115 i-cache-line-size = <64>;
116 i-cache-sets = <256>;
117 d-cache-size = <0x8000>;
118 d-cache-line-size = <64>;
119 d-cache-sets = <128>;
120 next-level-cache = <&cluster_a53_l2>;
125 compatible = "arm,cortex-a53";
126 enable-method = "psci";
128 clock-frequency = <1300000000>;
129 operating-points-v2 = <&cluster_a53_opp_table>;
130 #cooling-cells = <2>;
131 i-cache-size = <0x8000>;
132 i-cache-line-size = <64>;
133 i-cache-sets = <256>;
134 d-cache-size = <0x8000>;
135 d-cache-line-size = <64>;
136 d-cache-sets = <128>;
137 next-level-cache = <&cluster_a53_l2>;
142 compatible = "arm,cortex-a53";
143 enable-method = "psci";
145 clock-frequency = <1300000000>;
146 operating-points-v2 = <&cluster_a53_opp_table>;
147 #cooling-cells = <2>;
148 i-cache-size = <0x8000>;
149 i-cache-line-size = <64>;
150 i-cache-sets = <256>;
151 d-cache-size = <0x8000>;
152 d-cache-line-size = <64>;
153 d-cache-sets = <128>;
154 next-level-cache = <&cluster_a53_l2>;
159 compatible = "arm,cortex-a57";
160 enable-method = "psci";
162 clock-frequency = <1900000000>;
164 clock-names = "atlasclk";
165 operating-points-v2 = <&cluster_a57_opp_table>;
166 #cooling-cells = <2>;
167 i-cache-size = <0xc000>;
168 i-cache-line-size = <64>;
169 i-cache-sets = <256>;
170 d-cache-size = <0x8000>;
171 d-cache-line-size = <64>;
172 d-cache-sets = <256>;
173 next-level-cache = <&cluster_a57_l2>;
178 compatible = "arm,cortex-a57";
179 enable-method = "psci";
181 clock-frequency = <1900000000>;
182 operating-points-v2 = <&cluster_a57_opp_table>;
183 #cooling-cells = <2>;
184 i-cache-size = <0xc000>;
185 i-cache-line-size = <64>;
186 i-cache-sets = <256>;
187 d-cache-size = <0x8000>;
188 d-cache-line-size = <64>;
189 d-cache-sets = <256>;
190 next-level-cache = <&cluster_a57_l2>;
195 compatible = "arm,cortex-a57";
196 enable-method = "psci";
198 clock-frequency = <1900000000>;
199 operating-points-v2 = <&cluster_a57_opp_table>;
200 #cooling-cells = <2>;
201 i-cache-size = <0xc000>;
202 i-cache-line-size = <64>;
203 i-cache-sets = <256>;
204 d-cache-size = <0x8000>;
205 d-cache-line-size = <64>;
206 d-cache-sets = <256>;
207 next-level-cache = <&cluster_a57_l2>;
212 compatible = "arm,cortex-a57";
213 enable-method = "psci";
215 clock-frequency = <1900000000>;
216 operating-points-v2 = <&cluster_a57_opp_table>;
217 #cooling-cells = <2>;
218 i-cache-size = <0xc000>;
219 i-cache-line-size = <64>;
220 i-cache-sets = <256>;
221 d-cache-size = <0x8000>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <256>;
224 next-level-cache = <&cluster_a57_l2>;
227 cluster_a57_l2: l2-cache0 {
229 cache-size = <0x200000>;
230 cache-line-size = <64>;
231 cache-sets = <2048>;
234 cluster_a53_l2: l2-cache1 {
236 cache-size = <0x40000>;
237 cache-line-size = <64>;
238 cache-sets = <256>;
242 cluster_a53_opp_table: opp-table-0 {
243 compatible = "operating-points-v2";
244 opp-shared;
246 opp-400000000 {
247 opp-hz = /bits/ 64 <400000000>;
248 opp-microvolt = <900000>;
250 opp-500000000 {
251 opp-hz = /bits/ 64 <500000000>;
252 opp-microvolt = <925000>;
254 opp-600000000 {
255 opp-hz = /bits/ 64 <600000000>;
256 opp-microvolt = <950000>;
258 opp-700000000 {
259 opp-hz = /bits/ 64 <700000000>;
260 opp-microvolt = <975000>;
262 opp-800000000 {
263 opp-hz = /bits/ 64 <800000000>;
264 opp-microvolt = <1000000>;
266 opp-900000000 {
267 opp-hz = /bits/ 64 <900000000>;
268 opp-microvolt = <1050000>;
270 opp-1000000000 {
271 opp-hz = /bits/ 64 <1000000000>;
272 opp-microvolt = <1075000>;
274 opp-1100000000 {
275 opp-hz = /bits/ 64 <1100000000>;
276 opp-microvolt = <1112500>;
278 opp-1200000000 {
279 opp-hz = /bits/ 64 <1200000000>;
280 opp-microvolt = <1112500>;
282 opp-1300000000 {
283 opp-hz = /bits/ 64 <1300000000>;
284 opp-microvolt = <1150000>;
288 cluster_a57_opp_table: opp-table-1 {
289 compatible = "operating-points-v2";
290 opp-shared;
292 opp-500000000 {
293 opp-hz = /bits/ 64 <500000000>;
294 opp-microvolt = <900000>;
296 opp-600000000 {
297 opp-hz = /bits/ 64 <600000000>;
298 opp-microvolt = <900000>;
300 opp-700000000 {
301 opp-hz = /bits/ 64 <700000000>;
302 opp-microvolt = <912500>;
304 opp-800000000 {
305 opp-hz = /bits/ 64 <800000000>;
306 opp-microvolt = <912500>;
308 opp-900000000 {
309 opp-hz = /bits/ 64 <900000000>;
310 opp-microvolt = <937500>;
312 opp-1000000000 {
313 opp-hz = /bits/ 64 <1000000000>;
314 opp-microvolt = <975000>;
316 opp-1100000000 {
317 opp-hz = /bits/ 64 <1100000000>;
318 opp-microvolt = <1012500>;
320 opp-1200000000 {
321 opp-hz = /bits/ 64 <1200000000>;
322 opp-microvolt = <1037500>;
324 opp-1300000000 {
325 opp-hz = /bits/ 64 <1300000000>;
326 opp-microvolt = <1062500>;
328 opp-1400000000 {
329 opp-hz = /bits/ 64 <1400000000>;
330 opp-microvolt = <1087500>;
332 opp-1500000000 {
333 opp-hz = /bits/ 64 <1500000000>;
334 opp-microvolt = <1125000>;
336 opp-1600000000 {
337 opp-hz = /bits/ 64 <1600000000>;
338 opp-microvolt = <1137500>;
340 opp-1700000000 {
341 opp-hz = /bits/ 64 <1700000000>;
342 opp-microvolt = <1175000>;
344 opp-1800000000 {
345 opp-hz = /bits/ 64 <1800000000>;
346 opp-microvolt = <1212500>;
348 opp-1900000000 {
349 opp-hz = /bits/ 64 <1900000000>;
350 opp-microvolt = <1262500>;
362 compatible = "simple-bus";
363 #address-cells = <1>;
364 #size-cells = <1>;
368 compatible = "samsung,exynos4210-chipid";
372 cmu_top: clock-controller@10030000 {
373 compatible = "samsung,exynos5433-cmu-top";
375 #clock-cells = <1>;
377 clock-names = "oscclk",
387 cmu_cpif: clock-controller@10fc0000 {
388 compatible = "samsung,exynos5433-cmu-cpif";
390 #clock-cells = <1>;
392 clock-names = "oscclk";
396 cmu_mif: clock-controller@105b0000 {
397 compatible = "samsung,exynos5433-cmu-mif";
399 #clock-cells = <1>;
401 clock-names = "oscclk",
407 cmu_peric: clock-controller@14c80000 {
408 compatible = "samsung,exynos5433-cmu-peric";
410 #clock-cells = <1>;
413 cmu_peris: clock-controller@10040000 {
414 compatible = "samsung,exynos5433-cmu-peris";
416 #clock-cells = <1>;
419 cmu_fsys: clock-controller@156e0000 {
420 compatible = "samsung,exynos5433-cmu-fsys";
422 #clock-cells = <1>;
424 clock-names = "oscclk",
446 cmu_g2d: clock-controller@12460000 {
447 compatible = "samsung,exynos5433-cmu-g2d";
449 #clock-cells = <1>;
451 clock-names = "oscclk",
457 power-domains = <&pd_g2d>;
460 cmu_disp: clock-controller@13b90000 {
461 compatible = "samsung,exynos5433-cmu-disp";
463 #clock-cells = <1>;
465 clock-names = "oscclk",
483 power-domains = <&pd_disp>;
486 cmu_aud: clock-controller@114c0000 {
487 compatible = "samsung,exynos5433-cmu-aud";
489 #clock-cells = <1>;
490 clock-names = "oscclk", "fout_aud_pll";
492 power-domains = <&pd_aud>;
495 cmu_bus0: clock-controller@13600000 {
496 compatible = "samsung,exynos5433-cmu-bus0";
498 #clock-cells = <1>;
500 clock-names = "aclk_bus0_400";
504 cmu_bus1: clock-controller@14800000 {
505 compatible = "samsung,exynos5433-cmu-bus1";
507 #clock-cells = <1>;
509 clock-names = "aclk_bus1_400";
513 cmu_bus2: clock-controller@13400000 {
514 compatible = "samsung,exynos5433-cmu-bus2";
516 #clock-cells = <1>;
518 clock-names = "oscclk", "aclk_bus2_400";
522 cmu_g3d: clock-controller@14aa0000 {
523 compatible = "samsung,exynos5433-cmu-g3d";
525 #clock-cells = <1>;
527 clock-names = "oscclk", "aclk_g3d_400";
529 power-domains = <&pd_g3d>;
532 cmu_gscl: clock-controller@13cf0000 {
533 compatible = "samsung,exynos5433-cmu-gscl";
535 #clock-cells = <1>;
537 clock-names = "oscclk",
543 power-domains = <&pd_gscl>;
546 cmu_apollo: clock-controller@11900000 {
547 compatible = "samsung,exynos5433-cmu-apollo";
549 #clock-cells = <1>;
551 clock-names = "oscclk", "sclk_bus_pll_apollo";
555 cmu_atlas: clock-controller@11800000 {
556 compatible = "samsung,exynos5433-cmu-atlas";
558 #clock-cells = <1>;
560 clock-names = "oscclk", "sclk_bus_pll_atlas";
564 cmu_mscl: clock-controller@150d0000 {
565 compatible = "samsung,exynos5433-cmu-mscl";
567 #clock-cells = <1>;
569 clock-names = "oscclk",
575 power-domains = <&pd_mscl>;
578 cmu_mfc: clock-controller@15280000 {
579 compatible = "samsung,exynos5433-cmu-mfc";
581 #clock-cells = <1>;
583 clock-names = "oscclk", "aclk_mfc_400";
585 power-domains = <&pd_mfc>;
588 cmu_hevc: clock-controller@14f80000 {
589 compatible = "samsung,exynos5433-cmu-hevc";
591 #clock-cells = <1>;
593 clock-names = "oscclk", "aclk_hevc_400";
595 power-domains = <&pd_hevc>;
598 cmu_isp: clock-controller@146d0000 {
599 compatible = "samsung,exynos5433-cmu-isp";
601 #clock-cells = <1>;
603 clock-names = "oscclk",
609 power-domains = <&pd_isp>;
612 cmu_cam0: clock-controller@120d0000 {
613 compatible = "samsung,exynos5433-cmu-cam0";
615 #clock-cells = <1>;
617 clock-names = "oscclk",
625 power-domains = <&pd_cam0>;
628 cmu_cam1: clock-controller@145d0000 {
629 compatible = "samsung,exynos5433-cmu-cam1";
631 #clock-cells = <1>;
633 clock-names = "oscclk",
647 power-domains = <&pd_cam1>;
650 cmu_imem: clock-controller@11060000 {
651 compatible = "samsung,exynos5433-cmu-imem";
653 #clock-cells = <1>;
655 clock-names = "oscclk",
665 slim_sss: slim-sss@11140000 {
666 compatible = "samsung,exynos5433-slim-sss";
669 clock-names = "pclk", "aclk";
674 pd_gscl: power-domain@105c4000 {
675 compatible = "samsung,exynos5433-pd";
677 #power-domain-cells = <0>;
681 pd_cam0: power-domain@105c4020 {
682 compatible = "samsung,exynos5433-pd";
684 #power-domain-cells = <0>;
685 power-domains = <&pd_cam1>;
689 pd_mscl: power-domain@105c4040 {
690 compatible = "samsung,exynos5433-pd";
692 #power-domain-cells = <0>;
696 pd_g3d: power-domain@105c4060 {
697 compatible = "samsung,exynos5433-pd";
699 #power-domain-cells = <0>;
703 pd_disp: power-domain@105c4080 {
704 compatible = "samsung,exynos5433-pd";
706 #power-domain-cells = <0>;
710 pd_cam1: power-domain@105c40a0 {
711 compatible = "samsung,exynos5433-pd";
713 #power-domain-cells = <0>;
717 pd_aud: power-domain@105c40c0 {
718 compatible = "samsung,exynos5433-pd";
720 #power-domain-cells = <0>;
724 pd_g2d: power-domain@105c4120 {
725 compatible = "samsung,exynos5433-pd";
727 #power-domain-cells = <0>;
731 pd_isp: power-domain@105c4140 {
732 compatible = "samsung,exynos5433-pd";
734 #power-domain-cells = <0>;
735 power-domains = <&pd_cam0>;
739 pd_mfc: power-domain@105c4180 {
740 compatible = "samsung,exynos5433-pd";
742 #power-domain-cells = <0>;
746 pd_hevc: power-domain@105c41c0 {
747 compatible = "samsung,exynos5433-pd";
749 #power-domain-cells = <0>;
754 compatible = "samsung,exynos5433-tmu";
759 clock-names = "tmu_apbif", "tmu_sclk";
760 #thermal-sensor-cells = <0>;
765 compatible = "samsung,exynos5433-tmu";
770 clock-names = "tmu_apbif", "tmu_sclk";
771 #thermal-sensor-cells = <0>;
776 compatible = "samsung,exynos5433-tmu";
781 clock-names = "tmu_apbif", "tmu_sclk";
782 #thermal-sensor-cells = <0>;
787 compatible = "samsung,exynos5433-tmu";
792 clock-names = "tmu_apbif", "tmu_sclk";
793 #thermal-sensor-cells = <0>;
798 compatible = "samsung,exynos5433-tmu";
803 clock-names = "tmu_apbif", "tmu_sclk";
804 #thermal-sensor-cells = <0>;
809 compatible = "samsung,exynos5433-mct",
810 "samsung,exynos4210-mct";
825 clock-names = "fin_pll", "mct";
829 compatible = "samsung,exynos-ppmu-v2";
835 compatible = "samsung,exynos-ppmu-v2";
841 compatible = "samsung,exynos-ppmu-v2";
847 compatible = "samsung,exynos-ppmu-v2";
853 compatible = "samsung,exynos5433-pinctrl";
856 wakeup-interrupt-controller {
857 compatible = "samsung,exynos7-wakeup-eint";
863 compatible = "samsung,exynos5433-pinctrl";
866 power-domains = <&pd_aud>;
870 compatible = "samsung,exynos5433-pinctrl";
876 compatible = "samsung,exynos5433-pinctrl";
882 compatible = "samsung,exynos5433-pinctrl";
888 compatible = "samsung,exynos5433-pinctrl";
894 compatible = "samsung,exynos5433-pinctrl";
900 compatible = "samsung,exynos5433-pinctrl";
906 compatible = "samsung,exynos5433-pinctrl";
912 compatible = "samsung,exynos5433-pinctrl";
917 pmu_system_controller: system-controller@105c0000 {
918 compatible = "samsung,exynos5433-pmu", "syscon";
920 #clock-cells = <1>;
921 clock-names = "clkout16";
924 reboot: syscon-reboot {
925 compatible = "syscon-reboot";
932 gic: interrupt-controller@11001000 {
933 compatible = "arm,gic-400";
934 #interrupt-cells = <3>;
935 interrupt-controller;
943 mipi_phy: video-phy {
944 compatible = "samsung,exynos5433-mipi-video-phy";
945 #phy-cells = <1>;
946 samsung,pmu-syscon = <&pmu_system_controller>;
947 samsung,cam0-sysreg = <&syscon_cam0>;
948 samsung,cam1-sysreg = <&syscon_cam1>;
949 samsung,disp-sysreg = <&syscon_disp>;
953 compatible = "samsung,exynos5433-decon";
966 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
971 power-domains = <&pd_disp>;
972 interrupt-names = "fifo", "vsync", "lcd_sys";
976 samsung,disp-sysreg = <&syscon_disp>;
979 iommu-names = "m0", "m1";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 remote-endpoint =
996 compatible = "samsung,exynos5433-decon-tv";
1009 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1014 samsung,disp-sysreg = <&syscon_disp>;
1015 power-domains = <&pd_disp>;
1016 interrupt-names = "fifo", "vsync", "lcd_sys";
1022 iommu-names = "m0", "m1";
1026 compatible = "samsung,exynos5433-mipi-dsi";
1030 phy-names = "dsim";
1036 clock-names = "bus_clk",
1041 power-domains = <&pd_disp>;
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1053 remote-endpoint = <&mic_to_dsi>;
1060 compatible = "samsung,exynos5433-mic";
1064 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1065 power-domains = <&pd_disp>;
1066 samsung,disp-syscon = <&syscon_disp>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1076 remote-endpoint =
1084 remote-endpoint = <&dsi_to_mic>;
1091 compatible = "samsung,exynos5433-hdmi";
1103 clock-names = "hdmi_pclk", "hdmi_i_pclk",
1110 samsung,syscon-phandle = <&pmu_system_controller>;
1111 samsung,sysreg-phandle = <&syscon_disp>;
1112 #sound-dai-cells = <0>;
1121 compatible = "samsung,exynos5433-sysreg", "syscon";
1126 compatible = "samsung,exynos5433-sysreg", "syscon";
1131 compatible = "samsung,exynos5433-sysreg", "syscon";
1136 compatible = "samsung,exynos5433-sysreg", "syscon";
1140 gsc_0: video-scaler@13c00000 {
1141 compatible = "samsung,exynos5433-gsc";
1144 clock-names = "pclk", "aclk", "aclk_xiu",
1152 power-domains = <&pd_gscl>;
1155 gsc_1: video-scaler@13c10000 {
1156 compatible = "samsung,exynos5433-gsc";
1159 clock-names = "pclk", "aclk", "aclk_xiu",
1167 power-domains = <&pd_gscl>;
1170 gsc_2: video-scaler@13c20000 {
1171 compatible = "samsung,exynos5433-gsc";
1174 clock-names = "pclk", "aclk", "aclk_xiu",
1182 power-domains = <&pd_gscl>;
1186 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1191 interrupt-names = "job", "mmu", "gpu";
1193 clock-names = "core";
1194 power-domains = <&pd_g3d>;
1195 operating-points-v2 = <&gpu_opp_table>;
1198 gpu_opp_table: opp-table {
1199 compatible = "operating-points-v2";
1201 opp-160000000 {
1202 opp-hz = /bits/ 64 <160000000>;
1203 opp-microvolt = <1000000>;
1205 opp-267000000 {
1206 opp-hz = /bits/ 64 <267000000>;
1207 opp-microvolt = <1000000>;
1209 opp-350000000 {
1210 opp-hz = /bits/ 64 <350000000>;
1211 opp-microvolt = <1025000>;
1213 opp-420000000 {
1214 opp-hz = /bits/ 64 <420000000>;
1215 opp-microvolt = <1025000>;
1217 opp-500000000 {
1218 opp-hz = /bits/ 64 <500000000>;
1219 opp-microvolt = <1075000>;
1221 opp-550000000 {
1222 opp-hz = /bits/ 64 <550000000>;
1223 opp-microvolt = <1125000>;
1225 opp-600000000 {
1226 opp-hz = /bits/ 64 <600000000>;
1227 opp-microvolt = <1150000>;
1229 opp-700000000 {
1230 opp-hz = /bits/ 64 <700000000>;
1231 opp-microvolt = <1150000>;
1237 compatible = "samsung,exynos5433-scaler";
1240 clock-names = "pclk", "aclk", "aclk_xiu";
1245 power-domains = <&pd_mscl>;
1249 compatible = "samsung,exynos5433-scaler";
1252 clock-names = "pclk", "aclk", "aclk_xiu";
1257 power-domains = <&pd_mscl>;
1261 compatible = "samsung,exynos5433-jpeg";
1264 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1270 power-domains = <&pd_mscl>;
1274 compatible = "samsung,exynos5433-mfc";
1277 clock-names = "pclk", "aclk", "aclk_xiu";
1282 iommu-names = "left", "right";
1283 power-domains = <&pd_mfc>;
1287 compatible = "samsung,exynos-sysmmu";
1290 clock-names = "aclk", "pclk";
1293 power-domains = <&pd_disp>;
1294 #iommu-cells = <0>;
1298 compatible = "samsung,exynos-sysmmu";
1301 clock-names = "aclk", "pclk";
1304 #iommu-cells = <0>;
1305 power-domains = <&pd_disp>;
1309 compatible = "samsung,exynos-sysmmu";
1312 clock-names = "aclk", "pclk";
1315 #iommu-cells = <0>;
1316 power-domains = <&pd_disp>;
1320 compatible = "samsung,exynos-sysmmu";
1323 clock-names = "aclk", "pclk";
1326 #iommu-cells = <0>;
1327 power-domains = <&pd_disp>;
1331 compatible = "samsung,exynos-sysmmu";
1334 clock-names = "aclk", "pclk";
1337 #iommu-cells = <0>;
1338 power-domains = <&pd_gscl>;
1342 compatible = "samsung,exynos-sysmmu";
1345 clock-names = "aclk", "pclk";
1348 #iommu-cells = <0>;
1349 power-domains = <&pd_gscl>;
1353 compatible = "samsung,exynos-sysmmu";
1356 clock-names = "aclk", "pclk";
1359 #iommu-cells = <0>;
1360 power-domains = <&pd_gscl>;
1364 compatible = "samsung,exynos-sysmmu";
1367 clock-names = "aclk", "pclk";
1370 #iommu-cells = <0>;
1371 power-domains = <&pd_mscl>;
1375 compatible = "samsung,exynos-sysmmu";
1378 clock-names = "aclk", "pclk";
1381 #iommu-cells = <0>;
1382 power-domains = <&pd_mscl>;
1386 compatible = "samsung,exynos-sysmmu";
1389 clock-names = "aclk", "pclk";
1392 #iommu-cells = <0>;
1393 power-domains = <&pd_mscl>;
1397 compatible = "samsung,exynos-sysmmu";
1400 clock-names = "aclk", "pclk";
1403 #iommu-cells = <0>;
1404 power-domains = <&pd_mfc>;
1408 compatible = "samsung,exynos-sysmmu";
1411 clock-names = "aclk", "pclk";
1414 #iommu-cells = <0>;
1415 power-domains = <&pd_mfc>;
1419 compatible = "samsung,exynos5433-uart";
1424 clock-names = "uart", "clk_uart_baud0";
1425 pinctrl-names = "default";
1426 pinctrl-0 = <&uart0_bus>;
1431 compatible = "samsung,exynos5433-uart";
1436 clock-names = "uart", "clk_uart_baud0";
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&uart1_bus>;
1443 compatible = "samsung,exynos5433-uart";
1448 clock-names = "uart", "clk_uart_baud0";
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&uart2_bus>;
1455 compatible = "samsung,exynos5433-spi";
1459 dma-names = "tx", "rx";
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1465 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1466 samsung,spi-src-clk = <0>;
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&spi0_bus>;
1469 num-cs = <1>;
1474 compatible = "samsung,exynos5433-spi";
1478 dma-names = "tx", "rx";
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1484 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1485 samsung,spi-src-clk = <0>;
1486 pinctrl-names = "default";
1487 pinctrl-0 = <&spi1_bus>;
1488 num-cs = <1>;
1493 compatible = "samsung,exynos5433-spi";
1497 dma-names = "tx", "rx";
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1503 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1504 samsung,spi-src-clk = <0>;
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&spi2_bus>;
1507 num-cs = <1>;
1512 compatible = "samsung,exynos5433-spi";
1516 dma-names = "tx", "rx";
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1522 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1523 samsung,spi-src-clk = <0>;
1524 pinctrl-names = "default";
1525 pinctrl-0 = <&spi3_bus>;
1526 num-cs = <1>;
1531 compatible = "samsung,exynos5433-spi";
1535 dma-names = "tx", "rx";
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1541 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1542 samsung,spi-src-clk = <0>;
1543 pinctrl-names = "default";
1544 pinctrl-0 = <&spi4_bus>;
1545 num-cs = <1>;
1550 compatible = "samsung,exynos7-adc";
1553 clock-names = "adc";
1555 #io-channel-cells = <1>;
1560 compatible = "samsung,exynos7-i2s";
1563 dma-names = "tx", "rx";
1568 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1569 #clock-cells = <1>;
1570 #sound-dai-cells = <1>;
1575 compatible = "samsung,exynos4210-pwm";
1582 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1584 clock-names = "timers";
1585 #pwm-cells = <3>;
1590 compatible = "samsung,exynos7-hsi2c";
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1595 pinctrl-names = "default";
1596 pinctrl-0 = <&hs_i2c0_bus>;
1598 clock-names = "hsi2c";
1603 compatible = "samsung,exynos7-hsi2c";
1606 #address-cells = <1>;
1607 #size-cells = <0>;
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&hs_i2c1_bus>;
1611 clock-names = "hsi2c";
1616 compatible = "samsung,exynos7-hsi2c";
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&hs_i2c2_bus>;
1624 clock-names = "hsi2c";
1629 compatible = "samsung,exynos7-hsi2c";
1632 #address-cells = <1>;
1633 #size-cells = <0>;
1634 pinctrl-names = "default";
1635 pinctrl-0 = <&hs_i2c3_bus>;
1637 clock-names = "hsi2c";
1642 compatible = "samsung,exynos7-hsi2c";
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1647 pinctrl-names = "default";
1648 pinctrl-0 = <&hs_i2c4_bus>;
1650 clock-names = "hsi2c";
1655 compatible = "samsung,exynos7-hsi2c";
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1660 pinctrl-names = "default";
1661 pinctrl-0 = <&hs_i2c5_bus>;
1663 clock-names = "hsi2c";
1668 compatible = "samsung,exynos7-hsi2c";
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1673 pinctrl-names = "default";
1674 pinctrl-0 = <&hs_i2c6_bus>;
1676 clock-names = "hsi2c";
1681 compatible = "samsung,exynos7-hsi2c";
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&hs_i2c7_bus>;
1689 clock-names = "hsi2c";
1694 compatible = "samsung,exynos7-hsi2c";
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&hs_i2c8_bus>;
1702 clock-names = "hsi2c";
1707 compatible = "samsung,exynos7-hsi2c";
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1712 pinctrl-names = "default";
1713 pinctrl-0 = <&hs_i2c9_bus>;
1715 clock-names = "hsi2c";
1720 compatible = "samsung,exynos7-hsi2c";
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1725 pinctrl-names = "default";
1726 pinctrl-0 = <&hs_i2c10_bus>;
1728 clock-names = "hsi2c";
1733 compatible = "samsung,exynos7-hsi2c";
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&hs_i2c11_bus>;
1741 clock-names = "hsi2c";
1746 compatible = "samsung,exynos5433-dwusb3";
1751 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1752 #address-cells = <1>;
1753 #size-cells = <1>;
1762 clock-names = "ref", "bus_early", "suspend";
1766 phy-names = "usb2-phy", "usb3-phy";
1771 compatible = "samsung,exynos5433-usbdrd-phy";
1777 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1779 #phy-cells = <1>;
1780 samsung,pmu-syscon = <&pmu_system_controller>;
1785 compatible = "samsung,exynos5433-usbdrd-phy";
1791 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1793 #phy-cells = <1>;
1794 samsung,pmu-syscon = <&pmu_system_controller>;
1799 compatible = "samsung,exynos5433-dwusb3";
1804 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1805 #address-cells = <1>;
1806 #size-cells = <1>;
1815 clock-names = "ref", "bus_early", "suspend";
1819 phy-names = "usb2-phy", "usb3-phy";
1824 compatible = "samsung,exynos7-dw-mshc-smu";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1831 clock-names = "biu", "ciu";
1832 fifo-depth = <0x40>;
1837 compatible = "samsung,exynos7-dw-mshc-smu";
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1844 clock-names = "biu", "ciu";
1845 fifo-depth = <0x40>;
1850 compatible = "samsung,exynos7-dw-mshc-smu";
1852 #address-cells = <1>;
1853 #size-cells = <0>;
1857 clock-names = "biu", "ciu";
1858 fifo-depth = <0x40>;
1862 pdma0: dma-controller@15610000 {
1867 clock-names = "apb_pclk";
1868 #dma-cells = <1>;
1871 pdma1: dma-controller@15600000 {
1876 clock-names = "apb_pclk";
1877 #dma-cells = <1>;
1880 audio-subsystem@11400000 {
1881 compatible = "samsung,exynos5433-lpass";
1884 clock-names = "sfr0_ctrl";
1885 power-domains = <&pd_aud>;
1886 #address-cells = <1>;
1887 #size-cells = <1>;
1890 adma: dma-controller@11420000 {
1895 clock-names = "apb_pclk";
1896 #dma-cells = <1>;
1897 power-domains = <&pd_aud>;
1901 compatible = "samsung,exynos7-i2s";
1904 dma-names = "tx", "rx";
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1911 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1912 #clock-cells = <1>;
1913 pinctrl-names = "default";
1914 pinctrl-0 = <&i2s0_bus>;
1915 power-domains = <&pd_aud>;
1916 #sound-dai-cells = <1>;
1921 compatible = "samsung,exynos5433-uart";
1926 clock-names = "uart", "clk_uart_baud0";
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&uart_aud_bus>;
1929 power-domains = <&pd_aud>;
1934 pcie_phy: pcie-phy@15680000 {
1935 compatible = "samsung,exynos5433-pcie-phy";
1937 samsung,pmu-syscon = <&pmu_system_controller>;
1938 samsung,fsys-sysreg = <&syscon_fsys>;
1939 #phy-cells = <0>;
1944 compatible = "samsung,exynos5433-pcie";
1947 reg-names = "dbi", "elbi", "config";
1948 #address-cells = <3>;
1949 #size-cells = <2>;
1950 #interrupt-cells = <1>;
1955 clock-names = "pcie", "pcie_bus";
1956 num-lanes = <1>;
1957 num-viewport = <3>;
1958 bus-range = <0x00 0xff>;
1967 compatible = "arm,armv8-timer";
1979 #include "exynos5433-bus.dtsi"
1980 #include "exynos5433-pinctrl.dtsi"
1981 #include "exynos5433-tmu.dtsi"