Lines Matching +full:gic +full:- +full:its

4  *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
16 * * Neither the name of Broadcom nor the names of its
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
55 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 next-level-cache = <&CLUSTER0_L2>;
63 compatible = "arm,cortex-a72";
65 enable-method = "psci";
66 next-level-cache = <&CLUSTER1_L2>;
71 compatible = "arm,cortex-a72";
73 enable-method = "psci";
74 next-level-cache = <&CLUSTER1_L2>;
79 compatible = "arm,cortex-a72";
81 enable-method = "psci";
82 next-level-cache = <&CLUSTER2_L2>;
87 compatible = "arm,cortex-a72";
89 enable-method = "psci";
90 next-level-cache = <&CLUSTER2_L2>;
95 compatible = "arm,cortex-a72";
97 enable-method = "psci";
98 next-level-cache = <&CLUSTER3_L2>;
103 compatible = "arm,cortex-a72";
105 enable-method = "psci";
106 next-level-cache = <&CLUSTER3_L2>;
109 CLUSTER0_L2: l2-cache@0 {
113 CLUSTER1_L2: l2-cache@100 {
117 CLUSTER2_L2: l2-cache@200 {
121 CLUSTER3_L2: l2-cache@300 {
132 compatible = "arm,psci-0.2";
137 compatible = "arm,armv8-pmuv3";
142 compatible = "arm,armv8-timer";
150 compatible = "brcm,sr-mhb", "syscon";
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
161 compatible = "arm,ccn-502";
166 gic: interrupt-controller@2c00000 { label
167 compatible = "arm,gic-v3";
168 #interrupt-cells = <3>;
169 #address-cells = <1>;
170 #size-cells = <1>;
172 interrupt-controller;
177 gic_its: gic-its@63c20000 {
178 compatible = "arm,gic-v3-its";
179 msi-controller;
180 #msi-cells = <1>;
186 compatible = "arm,mmu-500";
188 #global-interrupts = <1>;
254 #iommu-cells = <2>;
259 compatible = "simple-bus";
260 #address-cells = <1>;
261 #size-cells = <1>;
264 #include "stingray-clock.dtsi"
267 compatible = "brcm,ocotp-v2";
269 brcm,ocotp-size = <2048>;
274 compatible = "brcm,sr-cdru", "syscon";
279 compatible = "brcm,iproc-gpio";
282 #gpio-cells = <2>;
283 gpio-controller;
287 #include "stingray-fs4.dtsi"
288 #include "stingray-pcie.dtsi"
289 #include "stingray-usb.dtsi"
292 compatible = "simple-bus";
293 #address-cells = <1>;
294 #size-cells = <1>;
297 #include "stingray-pinctrl.dtsi"
299 mdio_mux_iproc: mdio-mux@20000 {
300 compatible = "brcm,mdio-mux-iproc";
302 #address-cells = <1>;
303 #size-cells = <0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
313 #address-cells = <1>;
314 #size-cells = <0>;
319 #address-cells = <1>;
320 #size-cells = <0>;
325 compatible = "brcm,iproc-pwm";
328 #pwm-cells = <3>;
339 clock-names = "timer1", "timer2", "apb_pclk";
350 clock-names = "timer1", "timer2", "apb_pclk";
360 clock-names = "timer1", "timer2", "apb_pclk";
371 clock-names = "timer1", "timer2", "apb_pclk";
382 clock-names = "timer1", "timer2", "apb_pclk";
393 clock-names = "timer1", "timer2", "apb_pclk";
404 clock-names = "timer1", "timer2", "apb_pclk";
415 clock-names = "timer1", "timer2", "apb_pclk";
420 compatible = "brcm,iproc-i2c";
422 #address-cells = <1>;
423 #size-cells = <0>;
425 clock-frequency = <100000>;
434 clock-names = "wdog_clk", "apb_pclk";
435 timeout-sec = <60>;
439 compatible = "brcm,iproc-gpio";
442 #gpio-cells = <2>;
443 gpio-controller;
444 interrupt-controller;
446 gpio-ranges = <&pinmux 0 0 16>,
464 compatible = "brcm,iproc-i2c";
466 #address-cells = <1>;
467 #size-cells = <0>;
469 clock-frequency = <100000>;
475 compatible = "snps,dw-apb-uart";
477 reg-shift = <2>;
478 clock-frequency = <25000000>;
479 interrupt-parent = <&gic>;
486 compatible = "snps,dw-apb-uart";
488 reg-shift = <2>;
489 clock-frequency = <25000000>;
490 interrupt-parent = <&gic>;
497 compatible = "snps,dw-apb-uart";
499 reg-shift = <2>;
500 clock-frequency = <25000000>;
501 interrupt-parent = <&gic>;
508 compatible = "snps,dw-apb-uart";
510 reg-shift = <2>;
511 clock-frequency = <25000000>;
512 interrupt-parent = <&gic>;
522 clock-names = "sspclk", "apb_pclk";
523 num-cs = <1>;
524 #address-cells = <1>;
525 #size-cells = <0>;
534 clock-names = "sspclk", "apb_pclk";
535 num-cs = <1>;
536 #address-cells = <1>;
537 #size-cells = <0>;
542 compatible = "brcm,iproc-rng200";
546 dma0: dma-controller@310000 {
558 #dma-cells = <1>;
560 clock-names = "apb_pclk";
567 reg-names = "amac_base";
568 dma-coherent;
574 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
578 reg-names = "nand", "iproc-idm", "iproc-ext";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 brcm,nand-has-wp;
587 compatible = "brcm,sdhci-iproc";
590 bus-width = <8>;
597 compatible = "brcm,sdhci-iproc";
600 bus-width = <8>;
608 compatible = "simple-bus";
609 #address-cells = <1>;
610 #size-cells = <1>;
614 compatible = "brcm,sr-thermal";
616 brcm,tmon-mask = <0x3f>;
617 #thermal-sensor-cells = <1>;
621 thermal-zones {
622 ihost0_thermal: ihost0-thermal {
623 polling-delay-passive = <0>;
624 polling-delay = <1000>;
625 thermal-sensors = <&tmon 0>;
627 cpu-crit {
634 ihost1_thermal: ihost1-thermal {
635 polling-delay-passive = <0>;
636 polling-delay = <1000>;
637 thermal-sensors = <&tmon 1>;
639 cpu-crit {
646 ihost2_thermal: ihost2-thermal {
647 polling-delay-passive = <0>;
648 polling-delay = <1000>;
649 thermal-sensors = <&tmon 2>;
651 cpu-crit {
658 ihost3_thermal: ihost3-thermal {
659 polling-delay-passive = <0>;
660 polling-delay = <1000>;
661 thermal-sensors = <&tmon 3>;
663 cpu-crit {
670 crmu_thermal: crmu-thermal {
671 polling-delay-passive = <0>;
672 polling-delay = <1000>;
673 thermal-sensors = <&tmon 4>;
675 cpu-crit {
682 nitro_thermal: nitro-thermal {
683 polling-delay-passive = <0>;
684 polling-delay = <1000>;
685 thermal-sensors = <&tmon 5>;
687 cpu-crit {
696 nic-hsls {
697 compatible = "simple-bus";
698 #address-cells = <1>;
699 #size-cells = <1>;
703 compatible = "brcm,iproc-nic-i2c";
704 #address-cells = <1>;
705 #size-cells = <0>;
708 brcm,ape-hsls-addr-mask = <0x03400000>;
709 clock-frequency = <100000>;