Lines Matching +full:0 +full:x02c00000
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
109 CLUSTER0_L2: l2-cache@0 {
128 reg = <0x00000000 0x80000000 0 0x40000000>;
151 reg = <0 0x60401000 0 0x38c>;
158 ranges = <0x0 0x0 0x61000000 0x05000000>;
160 ccn: ccn@0 {
162 reg = <0x00000000 0x900000>;
173 reg = <0x02c00000 0x010000>, /* GICD */
174 <0x02e00000 0x600000>; /* GICR */
181 reg = <0x02c20000 0x10000>;
187 reg = <0x03000000 0x80000>;
262 ranges = <0x0 0x0 0x66400000 0x100000>;
268 reg = <0x0001c400 0x68>;
275 reg = <0x0001d000 0x400>;
280 reg = <0x00024800 0x4c>;
295 ranges = <0x0 0x0 0x68900000 0x17700000>;
301 reg = <0x00020000 0x250>;
303 #size-cells = <0>;
305 mdio@0 { /* PCIe serdes */
306 reg = <0x0>;
308 #size-cells = <0>;
312 reg = <0x3>;
314 #size-cells = <0>;
318 reg = <0x10>;
320 #size-cells = <0>;
326 reg = <0x00010000 0x1000>;
334 reg = <0x00030000 0x1000>;
345 reg = <0x00040000 0x1000>;
355 reg = <0x00050000 0x1000>;
366 reg = <0x00060000 0x1000>;
377 reg = <0x00070000 0x1000>;
388 reg = <0x00080000 0x1000>;
399 reg = <0x00090000 0x1000>;
410 reg = <0x000a0000 0x1000>;
421 reg = <0x000b0000 0x100>;
423 #size-cells = <0>;
431 reg = <0x000c0000 0x1000>;
440 reg = <0x000d0000 0x864>;
446 gpio-ranges = <&pinmux 0 0 16>,
465 reg = <0x000e0000 0x100>;
467 #size-cells = <0>;
476 reg = <0x00100000 0x1000>;
487 reg = <0x00110000 0x1000>;
498 reg = <0x00120000 0x1000>;
509 reg = <0x00130000 0x1000>;
519 reg = <0x00180000 0x1000>;
525 #size-cells = <0>;
531 reg = <0x00190000 0x1000>;
537 #size-cells = <0>;
543 reg = <0x00220000 0x28>;
548 reg = <0x00310000 0x1000>;
561 iommus = <&smmu 0x6000 0x0000>;
566 reg = <0x00340000 0x1000>;
575 reg = <0x00360000 0x600>,
576 <0x0050a408 0x600>,
577 <0x00360f00 0x20>;
581 #size-cells = <0>;
588 reg = <0x003f1000 0x100>;
592 iommus = <&smmu 0x6002 0x0000>;
598 reg = <0x003f2000 0x100>;
602 iommus = <&smmu 0x6003 0x0000>;
611 ranges = <0x0 0x0 0x8f100000 0x100>;
613 tmon: tmon@0 {
615 reg = <0x0 0x40>;
616 brcm,tmon-mask = <0x3f>;
623 polling-delay-passive = <0>;
625 thermal-sensors = <&tmon 0>;
629 hysteresis = <0>;
635 polling-delay-passive = <0>;
641 hysteresis = <0>;
647 polling-delay-passive = <0>;
653 hysteresis = <0>;
659 polling-delay-passive = <0>;
665 hysteresis = <0>;
671 polling-delay-passive = <0>;
677 hysteresis = <0>;
683 polling-delay-passive = <0>;
689 hysteresis = <0>;
700 ranges = <0x0 0x0 0x0 0x7fffffff>;
705 #size-cells = <0>;
706 reg = <0x60826100 0x100>,
707 <0x60e00408 0x1000>;
708 brcm,ape-hsls-addr-mask = <0x03400000>;