Lines Matching +full:0 +full:x66020000
33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
94 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
98 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
116 reg = <0 0x20020000 0 0x1000>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
123 linux,pci-domain = <0>;
125 bus-range = <0x00 0xff>;
130 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
134 brcm,pcie-ob-axi-offset = <0x00000000>;
147 reg = <0 0x50020000 0 0x1000>;
151 interrupt-map-mask = <0 0 0 0>;
152 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
156 bus-range = <0x00 0xff>;
161 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
165 brcm,pcie-ob-axi-offset = <0x30000000>;
178 reg = <0 0x60c00000 0 0x1000>;
182 bus-range = <0x0 0x1>;
187 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
198 ranges = <0 0 0 0xffffffff>;
204 reg = <0x61000000 0x1000>,
205 <0x61090000 0x1000>,
206 <0x61030000 0x100>;
217 reg = <0x612c0000 0x445>; /* PDC FS0 regs */
227 reg = <0x612d0000 0x900>;
228 mboxes = <&pdc0 0>;
233 reg = <0x612e0000 0x445>; /* PDC FS1 regs */
243 reg = <0x612f0000 0x900>;
244 mboxes = <&pdc1 0>;
249 reg = <0x61300000 0x445>; /* PDC FS2 regs */
259 reg = <0x61310000 0x900>;
260 mboxes = <&pdc2 0>;
265 reg = <0x61320000 0x445>; /* PDC FS3 regs */
275 reg = <0x61330000 0x900>;
276 mboxes = <&pdc3 0>;
281 reg = <0x61360000 0x1000>;
298 reg = <0x64000000 0x40000>;
339 reg = <0x6501d130 0x08>,
340 <0x660a0028 0x04>,
341 <0x660009b0 0x40>;
346 reg = <0x65024800 0x50>,
347 <0x65024008 0x18>;
357 reg = <0x65210000 0x1000>,
358 <0x65220000 0x1000>,
359 <0x65240000 0x2000>,
360 <0x65260000 0x1000>;
361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
366 ranges = <0 0x652e0000 0x80000>;
368 v2m0: v2m@0 {
372 reg = <0x00000 0x1000>;
381 reg = <0x10000 0x1000>;
390 reg = <0x20000 0x1000>;
399 reg = <0x30000 0x1000>;
408 reg = <0x40000 0x1000>;
417 reg = <0x50000 0x1000>;
426 reg = <0x60000 0x1000>;
435 reg = <0x70000 0x1000>;
445 reg = <0x65590000 0x1000>;
446 ranges = <0 0x65590000 0x10000>;
451 reg = <0x9000 0x4000>;
462 #phy-cells = <0>;
464 reg = <0x66000960 0x24>,
465 <0x67012800 0x4>,
466 <0x6501d148 0x4>,
467 <0x664d0700 0x4>;
470 id-gpios = <&gpio_g 30 0>;
471 vbus-gpios = <&gpio_g 31 0>;
477 reg = <0x66010000 0x28>;
485 reg = <0x66020000 0x250>;
487 #size-cells = <0>;
489 mdio@0 {
490 reg = <0x0>;
492 #size-cells = <0>;
494 pci_phy0: pci-phy@0 {
496 reg = <0x0>;
497 #phy-cells = <0>;
503 reg = <0x7>;
505 #size-cells = <0>;
507 pci_phy1: pci-phy@0 {
509 reg = <0x0>;
510 #phy-cells = <0>;
516 reg = <0x10>;
518 #size-cells = <0>;
524 reg = <0x66030000 0x1000>;
534 reg = <0x66040000 0x1000>;
544 reg = <0x66050000 0x1000>;
554 reg = <0x66060000 0x1000>;
564 reg = <0x66080000 0x100>;
566 #size-cells = <0>;
574 reg = <0x66090000 0x1000>;
582 reg = <0x660a0000 0x50>;
592 reg = <0x660b0000 0x100>;
594 #size-cells = <0>;
602 reg = <0x66100000 0x100>;
612 reg = <0x66110000 0x100>;
622 reg = <0x66120000 0x100>;
632 reg = <0x66130000 0x100>;
642 reg = <0x66180000 0x1000>;
647 #size-cells = <0>;
653 reg = <0x66190000 0x1000>;
658 #size-cells = <0>;
664 reg = <0x66220000 0x28>;
669 reg = <0x663f0100 0x1f00>,
670 <0x663f004c 0x10>;
673 #size-cells = <0>;
675 sata_phy0: sata-phy@0 {
676 reg = <0>;
677 #phy-cells = <0>;
683 #phy-cells = <0>;
690 reg = <0x663f2000 0x1000>;
695 #size-cells = <0>;
698 sata0: sata-port@0 {
699 reg = <0>;
713 reg = <0x66420000 0x100>;
723 reg = <0x66430000 0x100>;
733 reg = <0x66460000 0x600>,
734 <0x67015408 0x600>,
735 <0x66460f00 0x20>;
740 #size-cells = <0>;
747 reg = <0x66470200 0x184>,
748 <0x66470000 0x124>,
749 <0x67017408 0x004>,
750 <0x664703a0 0x01c>;
759 #size-cells = <0>;