Lines Matching +full:reg +full:- +full:io +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
24 reg = <0x0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a53";
31 reg = <0x1>;
32 enable-method = "psci";
36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
42 reg = <0x1 0x00000000 0x0 0x20000>;
43 no-map;
47 reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
48 no-map;
52 reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
53 no-map;
58 compatible = "arm,psci-0.2";
63 compatible = "arm,armv8-timer";
71 compatible = "fixed-clock";
72 clock-frequency = <25000000>;
73 #clock-cells = <0>;
77 compatible = "simple-bus";
78 #address-cells = <2>;
79 #size-cells = <2>;
82 gic: interrupt-controller@50001000 {
83 compatible = "arm,gic-400";
84 reg = <0x0 0x50001000 0x0 0x1000>,
87 interrupt-controller;
88 #interrupt-cells = <3>;
91 sctrl: system-controller@50010000 {
92 compatible = "bitmain,bm1880-sctrl", "syscon",
93 "simple-mfd";
94 reg = <0x0 0x50010000 0x0 0x1000>;
95 #address-cells = <1>;
96 #size-cells = <1>;
100 compatible = "bitmain,bm1880-pinctrl";
101 reg = <0x400 0x120>;
104 clk: clock-controller@e8 {
105 compatible = "bitmain,bm1880-clk";
106 reg = <0xe8 0x0c>, <0x800 0xb0>;
107 reg-names = "pll", "sys";
109 clock-names = "osc";
110 #clock-cells = <1>;
113 rst: reset-controller@c00 {
114 compatible = "bitmain,bm1880-reset";
115 reg = <0xc00 0x8>;
116 #reset-cells = <1>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "snps,dw-apb-gpio";
124 reg = <0x0 0x50027000 0x0 0x400>;
126 porta: gpio-controller@0 {
127 compatible = "snps,dw-apb-gpio-port";
128 gpio-controller;
129 #gpio-cells = <2>;
131 reg = <0>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "snps,dw-apb-gpio";
142 reg = <0x0 0x50027400 0x0 0x400>;
144 portb: gpio-controller@0 {
145 compatible = "snps,dw-apb-gpio-port";
146 gpio-controller;
147 #gpio-cells = <2>;
149 reg = <0>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "snps,dw-apb-gpio";
160 reg = <0x0 0x50027800 0x0 0x400>;
162 portc: gpio-controller@0 {
163 compatible = "snps,dw-apb-gpio-port";
164 gpio-controller;
165 #gpio-cells = <2>;
167 reg = <0>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
175 compatible = "snps,dw-apb-uart";
176 reg = <0x0 0x58018000 0x0 0x2000>;
179 clock-names = "baudclk", "apb_pclk";
181 reg-shift = <2>;
182 reg-io-width = <4>;
188 compatible = "snps,dw-apb-uart";
189 reg = <0x0 0x5801a000 0x0 0x2000>;
192 clock-names = "baudclk", "apb_pclk";
194 reg-shift = <2>;
195 reg-io-width = <4>;
201 compatible = "snps,dw-apb-uart";
202 reg = <0x0 0x5801c000 0x0 0x2000>;
205 clock-names = "baudclk", "apb_pclk";
207 reg-shift = <2>;
208 reg-io-width = <4>;
214 compatible = "snps,dw-apb-uart";
215 reg = <0x0 0x5801e000 0x0 0x2000>;
218 clock-names = "baudclk", "apb_pclk";
220 reg-shift = <2>;
221 reg-io-width = <4>;