Lines Matching +full:0 +full:x08
13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
55 gpios = <&iofpga_gpio0 0 0x4>;
62 gpios = <&iofpga_gpio0 1 0x4>;
69 gpios = <&iofpga_gpio0 2 0x4>;
76 gpios = <&iofpga_gpio0 3 0x4>;
83 gpios = <&iofpga_gpio0 4 0x4>;
90 gpios = <&iofpga_gpio0 5 0x4>;
98 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
104 ranges = <0 0 0 0x08000000 0x04000000>,
105 <1 0 0 0x14000000 0x04000000>,
106 <2 0 0 0x18000000 0x04000000>,
107 <3 0 0 0x1c000000 0x04000000>,
108 <4 0 0 0x0c000000 0x04000000>,
109 <5 0 0 0x10000000 0x04000000>;
110 arm,hbi = <0x252>;
111 arm,vexpress,site = <0>;
113 flash@0 {
116 reg = <0 0x00000000 0x04000000>;
132 reg = <2 0x00000000 0x10000>;
147 ranges = <0 3 0 0x200000>;
151 reg = <0x020000 0x1000>;
156 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
162 reg = <0x010000 0x1000>;
163 ranges = <0x0 0x10000 0x1000>;
167 led@8,0 {
169 reg = <0x08 0x04>;
170 offset = <0x08>;
171 mask = <0x01>;
172 label = "vexpress:0";
178 reg = <0x08 0x04>;
179 offset = <0x08>;
180 mask = <0x02>;
187 reg = <0x08 0x04>;
188 offset = <0x08>;
189 mask = <0x04>;
196 reg = <0x08 0x04>;
197 offset = <0x08>;
198 mask = <0x08>;
205 reg = <0x08 0x04>;
206 offset = <0x08>;
207 mask = <0x10>;
214 reg = <0x08 0x04>;
215 offset = <0x08>;
216 mask = <0x20>;
223 reg = <0x08 0x04>;
224 offset = <0x08>;
225 mask = <0x40>;
231 reg = <0x08 0x04>;
232 offset = <0x08>;
233 mask = <0x80>;
241 reg = <0x050000 0x1000>;
243 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
244 wp-gpios = <&v2m_mmc_gpios 1 0>; */
253 reg = <0x060000 0x1000>;
261 reg = <0x070000 0x1000>;
269 reg = <0x0f0000 0x10000>;
277 reg = <0x110000 0x10000>;
279 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
285 reg = <0x120000 0x10000>;
293 reg = <0x170000 0x10000>;
294 interrupts = <0>;
301 reg = <0x1d0000 0x1000>;