Lines Matching +full:t8103 +full:- +full:aic
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Apple T8103 "M1" SoC
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
29 enable-method = "spin-table";
30 cpu-release-addr = <0 0>; /* To be filled by loader */
37 enable-method = "spin-table";
38 cpu-release-addr = <0 0>; /* To be filled by loader */
45 enable-method = "spin-table";
46 cpu-release-addr = <0 0>; /* To be filled by loader */
53 enable-method = "spin-table";
54 cpu-release-addr = <0 0>; /* To be filled by loader */
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0>; /* To be filled by loader */
69 enable-method = "spin-table";
70 cpu-release-addr = <0 0>; /* To be filled by loader */
77 enable-method = "spin-table";
78 cpu-release-addr = <0 0>; /* To be filled by loader */
85 enable-method = "spin-table";
86 cpu-release-addr = <0 0>; /* To be filled by loader */
91 compatible = "arm,armv8-timer";
92 interrupt-parent = <&aic>;
93 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
100 pmu-e {
101 compatible = "apple,icestorm-pmu";
102 interrupt-parent = <&aic>;
106 pmu-p {
107 compatible = "apple,firestorm-pmu";
108 interrupt-parent = <&aic>;
112 clkref: clock-ref {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <24000000>;
116 clock-output-names = "clkref";
120 compatible = "simple-bus";
121 #address-cells = <2>;
122 #size-cells = <2>;
125 nonposted-mmio;
128 compatible = "apple,t8103-i2c", "apple,i2c";
131 interrupt-parent = <&aic>;
133 pinctrl-0 = <&i2c0_pins>;
134 pinctrl-names = "default";
135 #address-cells = <0x1>;
136 #size-cells = <0x0>;
137 power-domains = <&ps_i2c0>;
141 compatible = "apple,t8103-i2c", "apple,i2c";
144 interrupt-parent = <&aic>;
146 pinctrl-0 = <&i2c1_pins>;
147 pinctrl-names = "default";
148 #address-cells = <0x1>;
149 #size-cells = <0x0>;
150 power-domains = <&ps_i2c1>;
154 compatible = "apple,t8103-i2c", "apple,i2c";
157 interrupt-parent = <&aic>;
159 pinctrl-0 = <&i2c2_pins>;
160 pinctrl-names = "default";
161 #address-cells = <0x1>;
162 #size-cells = <0x0>;
164 power-domains = <&ps_i2c2>;
168 compatible = "apple,t8103-i2c", "apple,i2c";
171 interrupt-parent = <&aic>;
173 pinctrl-0 = <&i2c3_pins>;
174 pinctrl-names = "default";
175 #address-cells = <0x1>;
176 #size-cells = <0x0>;
177 power-domains = <&ps_i2c3>;
181 compatible = "apple,t8103-i2c", "apple,i2c";
184 interrupt-parent = <&aic>;
186 pinctrl-0 = <&i2c4_pins>;
187 pinctrl-names = "default";
188 #address-cells = <0x1>;
189 #size-cells = <0x0>;
190 power-domains = <&ps_i2c4>;
195 compatible = "apple,s5l-uart";
197 reg-io-width = <4>;
198 interrupt-parent = <&aic>;
205 clock-names = "uart", "clk_uart_baud0";
206 power-domains = <&ps_uart0>;
211 compatible = "apple,s5l-uart";
213 reg-io-width = <4>;
214 interrupt-parent = <&aic>;
217 clock-names = "uart", "clk_uart_baud0";
218 power-domains = <&ps_uart2>;
222 aic: interrupt-controller@23b100000 { label
223 compatible = "apple,t8103-aic", "apple,aic";
224 #interrupt-cells = <3>;
225 interrupt-controller;
227 power-domains = <&ps_aic>;
230 e-core-pmu-affinity {
231 apple,fiq-index = <AIC_CPU_PMU_E>;
235 p-core-pmu-affinity {
236 apple,fiq-index = <AIC_CPU_PMU_P>;
242 pmgr: power-management@23b700000 {
243 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
244 #address-cells = <1>;
245 #size-cells = <1>;
250 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
252 power-domains = <&ps_gpio>;
254 gpio-controller;
255 #gpio-cells = <2>;
256 gpio-ranges = <&pinctrl_ap 0 0 212>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 interrupt-parent = <&aic>;
270 i2c0_pins: i2c0-pins {
275 i2c1_pins: i2c1-pins {
280 i2c2_pins: i2c2-pins {
285 i2c3_pins: i2c3-pins {
290 i2c4_pins: i2c4-pins {
295 pcie_pins: pcie-pins {
303 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
305 power-domains = <&ps_nub_gpio>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 gpio-ranges = <&pinctrl_nub 0 0 23>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 interrupt-parent = <&aic>;
324 pmgr_mini: power-management@23d280000 {
325 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
326 #address-cells = <1>;
327 #size-cells = <1>;
332 compatible = "apple,t8103-wdt", "apple,wdt";
335 interrupt-parent = <&aic>;
340 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = <&pinctrl_smc 0 0 16>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 interrupt-parent = <&aic>;
361 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
364 gpio-controller;
365 #gpio-cells = <2>;
366 gpio-ranges = <&pinctrl_aop 0 0 42>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 interrupt-parent = <&aic>;
382 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
384 interrupt-parent = <&aic>;
389 interrupt-names = "send-empty", "send-not-empty",
390 "recv-empty", "recv-not-empty";
391 #mbox-cells = <0>;
392 power-domains = <&ps_ans2>;
396 compatible = "apple,t8103-sart";
398 power-domains = <&ps_ans2>;
402 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
405 reg-names = "nvme", "ans";
406 interrupt-parent = <&aic>;
410 power-domains = <&ps_ans2>, <&ps_apcie_st>;
411 power-domain-names = "ans", "apcie0";
416 compatible = "apple,t8103-dart";
418 #iommu-cells = <1>;
419 interrupt-parent = <&aic>;
421 power-domains = <&ps_apcie_gp>;
425 compatible = "apple,t8103-dart";
427 #iommu-cells = <1>;
428 interrupt-parent = <&aic>;
430 power-domains = <&ps_apcie_gp>;
434 compatible = "apple,t8103-dart";
436 #iommu-cells = <1>;
437 interrupt-parent = <&aic>;
439 power-domains = <&ps_apcie_gp>;
443 compatible = "apple,t8103-pcie", "apple,pcie";
451 reg-names = "config", "rc", "port0", "port1", "port2";
453 interrupt-parent = <&aic>;
458 msi-controller;
459 msi-parent = <&pcie0>;
460 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
463 iommu-map = <0x100 &pcie0_dart_0 1 1>,
466 iommu-map-mask = <0xff00>;
468 bus-range = <0 3>;
469 #address-cells = <3>;
470 #size-cells = <2>;
474 power-domains = <&ps_apcie_gp>;
475 pinctrl-0 = <&pcie_pins>;
476 pinctrl-names = "default";
481 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
483 #address-cells = <3>;
484 #size-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <1>;
490 interrupt-map-mask = <0 0 0 7>;
491 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
500 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
502 #address-cells = <3>;
503 #size-cells = <2>;
506 interrupt-controller;
507 #interrupt-cells = <1>;
509 interrupt-map-mask = <0 0 0 7>;
510 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
519 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
521 #address-cells = <3>;
522 #size-cells = <2>;
525 interrupt-controller;
526 #interrupt-cells = <1>;
528 interrupt-map-mask = <0 0 0 7>;
529 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
538 #include "t8103-pmgr.dtsi"