Lines Matching +full:0 +full:x4000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0 0x0>;
30 cpu-release-addr = <0 0>; /* To be filled by loader */
36 reg = <0x0 0x1>;
38 cpu-release-addr = <0 0>; /* To be filled by loader */
44 reg = <0x0 0x2>;
46 cpu-release-addr = <0 0>; /* To be filled by loader */
52 reg = <0x0 0x3>;
54 cpu-release-addr = <0 0>; /* To be filled by loader */
60 reg = <0x0 0x10100>;
62 cpu-release-addr = <0 0>; /* To be filled by loader */
68 reg = <0x0 0x10101>;
70 cpu-release-addr = <0 0>; /* To be filled by loader */
76 reg = <0x0 0x10102>;
78 cpu-release-addr = <0 0>; /* To be filled by loader */
84 reg = <0x0 0x10103>;
86 cpu-release-addr = <0 0>; /* To be filled by loader */
114 #clock-cells = <0>;
129 reg = <0x2 0x35010000 0x0 0x4000>;
133 pinctrl-0 = <&i2c0_pins>;
135 #address-cells = <0x1>;
136 #size-cells = <0x0>;
142 reg = <0x2 0x35014000 0x0 0x4000>;
146 pinctrl-0 = <&i2c1_pins>;
148 #address-cells = <0x1>;
149 #size-cells = <0x0>;
155 reg = <0x2 0x35018000 0x0 0x4000>;
159 pinctrl-0 = <&i2c2_pins>;
161 #address-cells = <0x1>;
162 #size-cells = <0x0>;
169 reg = <0x2 0x3501c000 0x0 0x4000>;
173 pinctrl-0 = <&i2c3_pins>;
175 #address-cells = <0x1>;
176 #size-cells = <0x0>;
182 reg = <0x2 0x35020000 0x0 0x4000>;
186 pinctrl-0 = <&i2c4_pins>;
188 #address-cells = <0x1>;
189 #size-cells = <0x0>;
196 reg = <0x2 0x35200000 0x0 0x1000>;
212 reg = <0x2 0x35208000 0x0 0x1000>;
226 reg = <0x2 0x3b100000 0x0 0x8000>;
246 reg = <0x2 0x3b700000 0 0x14000>;
251 reg = <0x2 0x3c100000 0x0 0x100000>;
256 gpio-ranges = <&pinctrl_ap 0 0 212>;
304 reg = <0x2 0x3d1f0000 0x0 0x4000>;
309 gpio-ranges = <&pinctrl_nub 0 0 23>;
328 reg = <0x2 0x3d280000 0 0x4000>;
333 reg = <0x2 0x3d2b0000 0x0 0x4000>;
341 reg = <0x2 0x3e820000 0x0 0x4000>;
345 gpio-ranges = <&pinctrl_smc 0 0 16>;
362 reg = <0x2 0x4a820000 0x0 0x4000>;
366 gpio-ranges = <&pinctrl_aop 0 0 42>;
383 reg = <0x2 0x77408000 0x0 0x4000>;
391 #mbox-cells = <0>;
397 reg = <0x2 0x7bc50000 0x0 0x10000>;
403 reg = <0x2 0x7bcc0000 0x0 0x40000>,
404 <0x2 0x77400000 0x0 0x4000>;
417 reg = <0x6 0x81008000 0x0 0x4000>;
426 reg = <0x6 0x82008000 0x0 0x4000>;
435 reg = <0x6 0x83008000 0x0 0x4000>;
446 reg = <0x6 0x90000000 0x0 0x1000000>,
447 <0x6 0x80000000 0x0 0x100000>,
448 <0x6 0x81000000 0x0 0x4000>,
449 <0x6 0x82000000 0x0 0x4000>,
450 <0x6 0x83000000 0x0 0x4000>;
463 iommu-map = <0x100 &pcie0_dart_0 1 1>,
464 <0x200 &pcie0_dart_1 1 1>,
465 <0x300 &pcie0_dart_2 1 1>;
466 iommu-map-mask = <0xff00>;
468 bus-range = <0 3>;
471 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
472 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
475 pinctrl-0 = <&pcie_pins>;
478 port00: pci@0,0 {
480 reg = <0x0 0x0 0x0 0x0 0x0>;
490 interrupt-map-mask = <0 0 0 7>;
491 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
492 <0 0 0 2 &port00 0 0 0 1>,
493 <0 0 0 3 &port00 0 0 0 2>,
494 <0 0 0 4 &port00 0 0 0 3>;
497 port01: pci@1,0 {
499 reg = <0x800 0x0 0x0 0x0 0x0>;
509 interrupt-map-mask = <0 0 0 7>;
510 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
511 <0 0 0 2 &port01 0 0 0 1>,
512 <0 0 0 3 &port01 0 0 0 2>,
513 <0 0 0 4 &port01 0 0 0 3>;
516 port02: pci@2,0 {
518 reg = <0x1000 0x0 0x0 0x0 0x0>;
528 interrupt-map-mask = <0 0 0 7>;
529 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
530 <0 0 0 2 &port02 0 0 0 1>,
531 <0 0 0 3 &port02 0 0 0 2>,
532 <0 0 0 4 &port02 0 0 0 3>;