Lines Matching +full:spin +full:- +full:table
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
25 #clock-cells = <1>;
32 enable-method = "spin-table";
33 cpu-release-addr = <0x1 0x0000fff8>;
34 next-level-cache = <&xgene_L2_0>;
35 #clock-cells = <1>;
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
44 next-level-cache = <&xgene_L2_1>;
45 #clock-cells = <1>;
52 enable-method = "spin-table";
53 cpu-release-addr = <0x1 0x0000fff8>;
54 next-level-cache = <&xgene_L2_1>;
55 #clock-cells = <1>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
65 #clock-cells = <1>;
72 enable-method = "spin-table";
73 cpu-release-addr = <0x1 0x0000fff8>;
74 next-level-cache = <&xgene_L2_2>;
75 #clock-cells = <1>;
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
84 next-level-cache = <&xgene_L2_3>;
85 #clock-cells = <1>;
92 enable-method = "spin-table";
93 cpu-release-addr = <0x1 0x0000fff8>;
94 next-level-cache = <&xgene_L2_3>;
95 #clock-cells = <1>;
98 xgene_L2_0: l2-cache-0 {
101 xgene_L2_1: l2-cache-1 {
104 xgene_L2_2: l2-cache-2 {
107 xgene_L2_3: l2-cache-3 {
112 gic: interrupt-controller@78090000 {
113 compatible = "arm,cortex-a15-gic";
114 #interrupt-cells = <3>;
115 #address-cells = <2>;
116 #size-cells = <2>;
117 interrupt-controller;
125 compatible = "arm,gic-v2m-frame";
126 msi-controller;
130 compatible = "arm,gic-v2m-frame";
131 msi-controller;
135 compatible = "arm,gic-v2m-frame";
136 msi-controller;
140 compatible = "arm,gic-v2m-frame";
141 msi-controller;
145 compatible = "arm,gic-v2m-frame";
146 msi-controller;
150 compatible = "arm,gic-v2m-frame";
151 msi-controller;
155 compatible = "arm,gic-v2m-frame";
156 msi-controller;
160 compatible = "arm,gic-v2m-frame";
161 msi-controller;
165 compatible = "arm,gic-v2m-frame";
166 msi-controller;
170 compatible = "arm,gic-v2m-frame";
171 msi-controller;
175 compatible = "arm,gic-v2m-frame";
176 msi-controller;
180 compatible = "arm,gic-v2m-frame";
181 msi-controller;
185 compatible = "arm,gic-v2m-frame";
186 msi-controller;
190 compatible = "arm,gic-v2m-frame";
191 msi-controller;
195 compatible = "arm,gic-v2m-frame";
196 msi-controller;
200 compatible = "arm,gic-v2m-frame";
201 msi-controller;
207 compatible = "arm,armv8-pmuv3";
212 compatible = "arm,armv8-timer";
214 <1 13 0xff08>, /* Non-secure Phys IRQ */
217 clock-frequency = <50000000>;
221 compatible = "simple-bus";
222 #address-cells = <2>;
223 #size-cells = <2>;
227 #address-cells = <2>;
228 #size-cells = <2>;
232 compatible = "fixed-clock";
233 #clock-cells = <1>;
234 clock-frequency = <100000000>;
235 clock-output-names = "refclk";
239 compatible = "apm,xgene-pcppll-v2-clock";
240 #clock-cells = <1>;
243 clock-output-names = "pmdpll";
247 compatible = "apm,xgene-pmd-clock";
248 #clock-cells = <1>;
251 clock-output-names = "pmd0clk";
255 compatible = "apm,xgene-pmd-clock";
256 #clock-cells = <1>;
259 clock-output-names = "pmd1clk";
263 compatible = "apm,xgene-pmd-clock";
264 #clock-cells = <1>;
267 clock-output-names = "pmd2clk";
271 compatible = "apm,xgene-pmd-clock";
272 #clock-cells = <1>;
275 clock-output-names = "pmd3clk";
279 compatible = "apm,xgene-socpll-v2-clock";
280 #clock-cells = <1>;
283 clock-output-names = "socpll";
287 compatible = "fixed-factor-clock";
288 #clock-cells = <1>;
290 clock-mult = <1>;
291 clock-div = <2>;
292 clock-output-names = "socplldiv2";
296 compatible = "apm,xgene-device-clock";
297 #clock-cells = <1>;
300 reg-names = "div-reg";
301 divider-offset = <0x164>;
302 divider-width = <0x5>;
303 divider-shift = <0x0>;
304 clock-output-names = "ahbclk";
308 compatible = "apm,xgene-device-clock";
309 #clock-cells = <1>;
312 reg-names = "div-reg";
313 divider-offset = <0x10>;
314 divider-width = <0x2>;
315 divider-shift = <0x0>;
316 clock-output-names = "sbapbclk";
320 compatible = "apm,xgene-device-clock";
321 #clock-cells = <1>;
325 reg-names = "csr-reg", "div-reg";
326 csr-offset = <0x0>;
327 csr-mask = <0x2>;
328 enable-offset = <0x8>;
329 enable-mask = <0x2>;
330 divider-offset = <0x178>;
331 divider-width = <0x8>;
332 divider-shift = <0x0>;
333 clock-output-names = "sdioclk";
337 compatible = "apm,xgene-device-clock";
338 #clock-cells = <1>;
341 reg-names = "csr-reg";
342 clock-output-names = "pcie0clk";
346 compatible = "apm,xgene-device-clock";
347 #clock-cells = <1>;
350 reg-names = "csr-reg";
351 clock-output-names = "pcie1clk";
355 compatible = "apm,xgene-device-clock";
356 #clock-cells = <1>;
359 reg-names = "csr-reg";
360 enable-mask = <0x3>;
361 csr-mask = <0x3>;
362 clock-output-names = "xge0clk";
366 compatible = "apm,xgene-device-clock";
367 #clock-cells = <1>;
370 reg-names = "csr-reg";
371 enable-mask = <0x3>;
372 csr-mask = <0x3>;
373 clock-output-names = "xge1clk";
377 compatible = "apm,xgene-device-clock";
378 #clock-cells = <1>;
381 reg-names = "csr-reg";
382 csr-offset = <0xc>;
383 csr-mask = <0x10>;
384 enable-offset = <0x10>;
385 enable-mask = <0x10>;
386 clock-output-names = "rngpkaclk";
390 compatible = "apm,xgene-device-clock";
391 #clock-cells = <1>;
394 reg-names = "csr-reg";
395 csr-offset = <0x0>;
396 csr-mask = <0x40>;
397 enable-offset = <0x8>;
398 enable-mask = <0x40>;
399 clock-output-names = "i2c4clk";
403 scu: system-clk-controller@17000000 {
404 compatible = "apm,xgene-scu","syscon";
409 compatible = "syscon-reboot";
416 compatible = "apm,xgene-csw", "syscon";
421 compatible = "apm,xgene-mcb", "syscon";
426 compatible = "apm,xgene-mcb", "syscon";
431 compatible = "apm,xgene-efuse", "syscon";
436 compatible = "apm,xgene-edac";
437 #address-cells = <2>;
438 #size-cells = <2>;
440 regmap-csw = <&csw>;
441 regmap-mcba = <&mcba>;
442 regmap-mcbb = <&mcbb>;
443 regmap-efuse = <&efuse>;
450 compatible = "apm,xgene-edac-mc";
452 memory-controller = <0>;
456 compatible = "apm,xgene-edac-mc";
458 memory-controller = <1>;
462 compatible = "apm,xgene-edac-mc";
464 memory-controller = <2>;
468 compatible = "apm,xgene-edac-mc";
470 memory-controller = <3>;
474 compatible = "apm,xgene-edac-pmd";
476 pmd-controller = <0>;
480 compatible = "apm,xgene-edac-pmd";
482 pmd-controller = <1>;
486 compatible = "apm,xgene-edac-pmd";
488 pmd-controller = <2>;
492 compatible = "apm,xgene-edac-pmd";
494 pmd-controller = <3>;
498 compatible = "apm,xgene-edac-l3-v2";
503 compatible = "apm,xgene-edac-soc";
509 compatible = "apm,xgene-pmu-v2";
510 #address-cells = <2>;
511 #size-cells = <2>;
513 regmap-csw = <&csw>;
514 regmap-mcba = <&mcba>;
515 regmap-mcbb = <&mcbb>;
520 compatible = "apm,xgene-pmu-l3c";
525 compatible = "apm,xgene-pmu-iob";
530 compatible = "apm,xgene-pmu-mcb";
532 enable-bit-index = <0>;
536 compatible = "apm,xgene-pmu-mcb";
538 enable-bit-index = <1>;
542 compatible = "apm,xgene-pmu-mc";
544 enable-bit-index = <0>;
548 compatible = "apm,xgene-pmu-mc";
550 enable-bit-index = <1>;
554 compatible = "apm,xgene-pmu-mc";
556 enable-bit-index = <2>;
560 compatible = "apm,xgene-pmu-mc";
562 enable-bit-index = <3>;
567 compatible = "apm,xgene-slimpro-mbox";
569 #mbox-cells = <1>;
581 compatible = "apm,xgene-slimpro-i2c";
586 compatible = "apm,xgene-slimpro-hwmon";
594 reg-shift = <2>;
595 clock-frequency = <10000000>;
596 interrupt-parent = <&gic>;
600 /* Node-name might need to be coded as dwusb for backward compatibility */
606 dma-coherent;
613 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
614 #interrupt-cells = <1>;
615 #size-cells = <2>;
616 #address-cells = <3>;
619 reg-names = "csr", "cfg";
623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
625 bus-range = <0x00 0xff>;
626 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
631 dma-coherent;
633 msi-parent = <&v2m0>;
639 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
640 #interrupt-cells = <1>;
641 #size-cells = <2>;
642 #address-cells = <3>;
645 reg-names = "csr", "cfg";
649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
651 bus-range = <0x00 0xff>;
652 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
657 dma-coherent;
659 msi-parent = <&v2m0>;
663 compatible = "apm,xgene-ahci-v2";
669 dma-coherent;
673 compatible = "apm,xgene-ahci-v2";
679 dma-coherent;
683 compatible = "apm,xgene-ahci-v2";
689 dma-coherent;
693 compatible = "arasan,sdhci-4.9a";
696 dma-coherent;
697 no-1-8-v;
698 clock-names = "clk_xin", "clk_ahb";
703 compatible = "apm,xgene-gpio";
705 gpio-controller;
706 #gpio-cells = <2>;
710 compatible = "snps,dw-apb-gpio";
712 #address-cells = <1>;
713 #size-cells = <0>;
715 porta: gpio-controller@0 {
716 compatible = "snps,dw-apb-gpio-port";
717 gpio-controller;
718 #gpio-cells = <2>;
719 snps,nr-gpios = <32>;
725 compatible = "apm,xgene-gpio-sb";
727 #gpio-cells = <2>;
728 gpio-controller;
737 interrupt-parent = <&gic>;
738 #interrupt-cells = <2>;
739 interrupt-controller;
740 apm,nr-gpios = <22>;
741 apm,nr-irqs = <8>;
742 apm,irq-start = <8>;
746 compatible = "apm,xgene-mdio-xfi";
747 #address-cells = <1>;
748 #size-cells = <0>;
754 compatible = "apm,xgene2-sgenet";
761 dma-coherent;
763 local-mac-address = [00 01 73 00 00 01];
764 phy-connection-type = "sgmii";
765 phy-handle = <&sgenet0phy>;
769 compatible = "apm,xgene2-xgenet";
783 port-id = <1>;
784 dma-coherent;
786 local-mac-address = [00 01 73 00 00 02];
787 phy-connection-type = "xgmii";
791 compatible = "apm,xgene-rng";
798 #address-cells = <1>;
799 #size-cells = <0>;
800 compatible = "snps,designware-i2c";
803 #clock-cells = <1>;
809 #address-cells = <1>;
810 #size-cells = <0>;
811 compatible = "snps,designware-i2c";