Lines Matching +full:synquacer +full:- +full:pre +full:- +full:its
1 # SPDX-License-Identifier: GPL-2.0-only
234 ARM 64-bit (AArch64) Linux support.
244 depends on $(cc-option,-fpatchable-function-entry=2)
277 # VA_BITS - PAGE_SHIFT - 3
356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
383 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
397 data cache clean-and-invalidate.
405 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
410 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
419 data cache clean-and-invalidate.
427 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
432 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
435 If a Cortex-A53 processor is executing a store or prefetch for
442 data cache clean-and-invalidate.
450 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
455 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
464 data cache clean-and-invalidate.
472 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
476 erratum 832075 on Cortex-A57 parts up to r1p2.
478 Affected Cortex-A57 parts might deadlock when exclusive load/store
479 instructions to Write-Back memory are mixed with Device loads.
481 The workaround is to promote device loads to use Load-Acquire
490 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
495 erratum 834220 on Cortex-A57 parts up to r1p2.
497 Affected Cortex-A57 parts might report a Stage 2 translation
511 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
515 This option removes the AES hwcap for aarch32 user-space to
516 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
527 bool "Cortex-A53: 845719: a load might read incorrect data"
532 erratum 845719 on Cortex-A53 parts up to r0p4.
534 When running a compat (AArch32) userspace on an affected Cortex-A53
540 return to a 32-bit task.
548 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
552 This option links the kernel with '--fix-cortex-a53-843419' and
555 Cortex-A53 parts up to r0p4.
560 def_bool $(ld-option,--fix-cortex-a53-843419)
563 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
566 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
568 Affected Cortex-A55 cores (all revisions) could cause incorrect
570 without a break-before-make. The workaround is to disable the usage
577 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
581 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
584 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
594 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
598 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
600 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
607 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
611 This option adds work arounds for ARM Cortex-A57 erratum 1319537
614 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
620 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
624 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
626 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
636 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
640 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
642 Under very rare circumstances, affected Cortex-A55 CPUs
643 may not handle a race between a break-before-make sequence on one
653 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
657 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
659 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
663 break-before-make sequence, then under very rare circumstances
669 bool "Cortex-A76: Software Step might prevent interrupt recognition"
672 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
674 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
687 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
690 This option adds a workaround for ARM Neoverse-N1 erratum
693 Affected Neoverse-N1 cores could execute a stale instruction when
698 forces user-space to perform cache maintenance.
703 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
706 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
708 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
709 of a store-exclusive or read of PAR_EL1 and a load with device or
710 non-cacheable memory attributes. The workaround depends on a firmware
726 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
729 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
730 Affected Cortex-A510 might not respect the ordering rules for
737 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
740 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
741 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
749 previous guest entry, and can be restored from the in-memory copy.
754 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
757 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
758 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
762 user-space should not be using these instructions.
767 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
772 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
774 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
785 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
790 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
792 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
806 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
810 Enable workaround for ARM Cortex-A710 erratum 2054223
821 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
825 Enable workaround for ARM Neoverse-N2 erratum 2067961
839 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
844 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
846 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
857 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
862 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
864 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
875 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
879 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
881 Under very rare circumstances, affected Cortex-A510 CPUs
882 may not handle a race between a break-before-make sequence on one
892 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
896 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
898 Affected Cortex-A510 core might fail to write into system registers after the
910 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
914 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
916 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
933 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
937 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
939 Affected Cortex-A510 core might cause trace data corruption, when being written
951 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
955 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
958 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
973 This implements two gicv3-its errata workarounds for ThunderX. Both
974 with a small impact affecting only ITS table allocation.
979 The fixes are in ITS initialization and basically ignore memory access
985 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
989 ITS SYNC command hang for cross node io and collections/cpu mapping.
1013 contains data for a non-current ASID. The fix is to
1024 interrupts in host. Trapping both GICv3 group-0 and group-1
1047 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1050 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1051 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1055 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1056 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1057 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1058 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1061 The workaround only affects the Fujitsu-A64FX.
1070 when issued ITS commands such as VMOVP and VMAPP, and requires
1101 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1121 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1128 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1131 Socionext Synquacer SoCs implement a separate h/w block to generate
1132 MSI doorbell writes with non-zero values for the device ID.
1161 look-up. AArch32 emulation requires applications compiled
1177 bool "36-bit" if EXPERT
1181 bool "39-bit"
1185 bool "42-bit"
1189 bool "47-bit"
1193 bool "48-bit"
1196 bool "52-bit"
1199 Enable 52-bit virtual addressing for userspace when explicitly
1200 requested via a hint to mmap(). The kernel will also use 52-bit
1201 virtual addresses for its own mappings (provided HW support for
1202 this feature is available, otherwise it reverts to 48-bit).
1204 NOTE: Enabling 52-bit virtual addressing in conjunction with
1207 impact on its susceptibility to brute-force attacks.
1209 If unsure, select 48-bit virtual addressing instead.
1214 bool "Force 52-bit virtual addresses for userspace"
1217 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1218 to maintain compatibility with older software by providing 48-bit VAs
1221 This configuration option disables the 48-bit compatibility logic, and
1222 forces all userspace addresses to be 52-bit on HW that supports it. One
1243 bool "48-bit"
1246 bool "52-bit (ARMv8.2)"
1250 Enable support for a 52-bit physical address space, introduced as
1251 part of the ARMv8.2-LPA extension.
1254 do not support ARMv8.2-LPA, but with some added memory overhead (and
1273 bool "Build big-endian kernel"
1276 Say Y if you plan on running a kernel with a big-endian userspace.
1279 bool "Build little-endian kernel"
1281 Say Y if you plan on running a kernel with a little-endian userspace.
1287 bool "Multi-core scheduler support"
1289 Multi-core scheduler support improves the CPU scheduler's decision
1290 making when dealing with multi-core CPU chips at a cost of slightly
1299 by sharing mid-level caches, last-level cache tags or internal
1310 int "Maximum number of CPUs (2-4096)"
1315 bool "Support for hot-pluggable CPUs"
1332 Enable NUMA (Non-Uniform Memory Access) support.
1360 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1429 loaded in the main kernel with kexec-tools into a specially
1433 For more details see Documentation/admin-guide/kdump/kdump.rst
1469 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1478 Speculation attacks against some high-performance processors can
1490 Speculation attacks against some high-performance processors can
1492 When taking an exception from user-space, a sequence of branches
1499 Apply read-only attributes of VM areas to the linear alias of
1500 the backing pages as well. This prevents code or read-only data
1513 user-space memory directly by pointing TTBR0_EL1 to a reserved
1524 Documentation/arm64/tagged-address-abi.rst.
1527 bool "Kernel support for 32-bit EL0"
1533 This option enables support for a 32-bit EL0 running under a 64-bit
1534 kernel at EL1. AArch32-specific components such as system calls,
1542 If you want to execute 32-bit userspace applications, say Y.
1547 bool "Enable kuser helpers page for 32-bit applications"
1550 Warning: disabling this option may break 32-bit user programs.
1574 bool "Enable vDSO for 32-bit applications"
1580 Place in the process address space of 32-bit applications an
1584 You must have a 32-bit build of glibc 2.22 or later for programs
1588 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1592 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1593 otherwise with '-marm'.
1596 bool "Fix up misaligned multi-word loads and stores in user space"
1638 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1639 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1654 The SETEND instruction alters the data-endianness of the
1662 for this feature to be enabled. If a new CPU - which doesn't support mixed
1663 endian - is hotplugged in after this feature has been enabled, there could
1682 Similarly, writes to read-only pages with the DBM bit set will
1683 clear the read-only bit (AP[2]) instead of raising a
1687 to work on pre-ARMv8.1 hardware and the performance impact is
1695 prevents the kernel or hypervisor from accessing user-space (EL0)
1705 def_bool $(as-instr,.arch_extension rcpc)
1708 def_bool $(as-instr,.arch_extension lse)
1724 Say Y here to make use of these instructions for the in-kernel
1735 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1738 def_bool $(as-instr,.arch armv8.2-a+sha3)
1798 context-switched along with the process.
1821 If the compiler supports the -mbranch-protection or
1822 -msign-return-address flag (e.g. GCC 7 or later), then this option
1833 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1837 def_bool $(cc-option,-msign-return-address=all)
1840 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1843 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1873 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1880 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1891 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1925 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1936 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1952 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1956 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1970 architectural support for run-time, always-on detection of
1972 to eliminate vulnerabilities arising from memory-unsafe
1980 not be allowed a late bring-up.
1986 Documentation/arm64/memory-tagging-extension.rst.
1998 Access Never to be used with Execute-only mappings.
2029 If you need the kernel to boot on SVE-capable hardware with broken
2067 bool "Support for NMI-like interrupts"
2070 Adds support for mimicking Non-Maskable Interrupts through the use of
2114 random u64 value in /chosen/kaslr-seed at kernel entry.
2142 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2177 Provide a set of default command-line options at build time by
2191 Uses the command-line options passed by the boot loader. If
2201 command-line options your boot loader passes to the kernel.
2223 by UEFI firmware (such as non-volatile variables, realtime
2237 continue to boot on existing non-UEFI platforms.