Lines Matching full:affected
400 the kernel if an affected CPU is detected.
422 the kernel if an affected CPU is detected.
445 only patch the kernel if an affected CPU is detected.
467 the kernel if an affected CPU is detected.
478 Affected Cortex-A57 parts might deadlock when exclusive load/store
485 the kernel if an affected CPU is detected.
497 Affected Cortex-A57 parts might report a Stage 2 translation
506 the kernel if an affected CPU is detected.
518 Affected parts may corrupt the AES state if an interrupt is
534 When running a compat (AArch32) userspace on an affected Cortex-A53
543 the kernel if an affected CPU is detected.
568 Affected Cortex-A55 cores (all revisions) could cause incorrect
571 of hardware DBM locally on the affected cores. CPUs not affected by
584 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
600 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
626 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
636 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
642 Under very rare circumstances, affected Cortex-A55 CPUs
647 Work around this by adding the affected CPUs to the list that needs
659 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
674 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
693 Affected Neoverse-N1 cores could execute a stale instruction when
708 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
730 Affected Cortex-A510 might not respect the ordering rules for
732 is to not enable the feature on affected CPUs.
741 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
758 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
774 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
792 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
812 Affected cores may fail to flush the trace data on a TSB instruction, when
816 Workaround is to issue two TSB consecutively on affected cores.
827 Affected cores may fail to flush the trace data on a TSB instruction, when
831 Workaround is to issue two TSB consecutively on affected cores.
846 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
864 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
875 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
881 Under very rare circumstances, affected Cortex-A510 CPUs
886 Work around this by adding the affected CPUs to the list that needs
898 Affected Cortex-A510 core might fail to write into system registers after the
904 is stopped and before performing a system register write to one of the affected
916 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
939 Affected Cortex-A510 core might cause trace data corruption, when being written
944 affected cpus. The firmware must have disabled the access to TRBE for the kernel
958 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
961 Work around this problem by returning 0 when reading the affected counter in
963 is the same to firmware disabling affected counters.