Lines Matching full:r0
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x00001000 @ i-cache
45 bic r0, r0, #0x00000004 @ d-cache
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 * Params : r0 = address to jump to
64 ret r0
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
82 mov r0, #0
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
131 sub r3, r1, r0 @ calculate total size
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
139 add r0, r0, #CACHE_DLINESIZE
140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 add r0, r0, #CACHE_DLINESIZE
144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 add r0, r0, #CACHE_DLINESIZE
147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
149 add r0, r0, #CACHE_DLINESIZE
151 cmp r0, r1
182 bic r0, r0, #CACHE_DLINESIZE - 1
183 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
185 add r0, r0, #CACHE_DLINESIZE
186 cmp r0, r1
188 mcr p15, 0, r0, c7, c10, 4 @ drain WB
189 mov r0, #0
203 add r1, r0, r1
204 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
205 add r0, r0, #CACHE_DLINESIZE
206 cmp r0, r1
208 mov r0, #0
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c10, 4 @ drain WB
227 tst r0, #CACHE_DLINESIZE - 1
228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
232 bic r0, r0, #CACHE_DLINESIZE - 1
233 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
234 add r0, r0, #CACHE_DLINESIZE
235 cmp r0, r1
237 mcr p15, 0, r0, c7, c10, 4 @ drain WB
252 bic r0, r0, #CACHE_DLINESIZE - 1
253 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
254 add r0, r0, #CACHE_DLINESIZE
255 cmp r0, r1
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
272 bic r0, r0, #CACHE_DLINESIZE - 1
275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
277 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
279 add r0, r0, #CACHE_DLINESIZE
280 cmp r0, r1
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
292 add r1, r1, r0
317 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
318 add r0, r0, #CACHE_DLINESIZE
322 mcr p15, 0, r0, c7, c10, 4 @ drain WB
327 mov r0, #0
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
329 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
330 mcr p15, 0, r0, c7, c10, 4 @ drain WB
332 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
333 mcr p15, 0, r0, c6, c4, 0
334 mcr p15, 0, r0, c6, c5, 0
335 mcr p15, 0, r0, c6, c6, 0
336 mcr p15, 0, r0, c6, c7, 0
338 mov r0, #0x0000003F @ base = 0, size = 4GB
339 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
341 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
343 pr_val r3, r0, r7, #1
346 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
348 pr_val r3, r0, r7, #1
351 mov r0, #0x06
352 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
353 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
355 mov r0, #0x00 @ disable whole write buffer
357 mov r0, #0x02 @ region 1 write bufferred
359 mcr p15, 0, r0, c3, c0, 0
370 mov r0, #0x00000031
371 orr r0, r0, #0x00000200
372 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
373 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
375 mrc p15, 0, r0, c1, c0 @ get control register
376 orr r0, r0, #0x00001000 @ I-cache
377 orr r0, r0, #0x00000005 @ MPU/D-cache
379 orr r0, r0, #0x00004000 @ .1.. .... .... ....