Lines Matching full:clean
22 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
27 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
65 * clean the whole cache, rather than using the individual
139 * Unconditionally clean and invalidate the entire icache.
150 * Clean and invalidate all cache entries in a particular
159 * Clean and invalidate the entire cache.
170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
182 * Clean and invalidate a range of cache entries in the
203 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
206 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
241 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
261 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
288 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
301 * Clean the specified virtual address range.
311 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 * Clean and invalidate the specified virtual address range.
331 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
373 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
399 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
431 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */