Lines Matching refs:ldr
82 ldr \rd, [\base, #EMC_ADR_CFG]
92 ldr \rd, [\base, #EMC_EMC_STATUS]
98 ldr \rd, tegra_pll_state
103 ldr \rd, [\r_car_base, #\pll_base]
105 ldr \rd, tegra_pll_state
113 ldr \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
115 ldr \rd, tegra_pll_state
134 ldr \rd, [\r_car_base, #\pll_base]
140 ldr \rd, [\r_car_base, #\pll_misc]
143 ldr \rd, [\r_car_base, #\pll_misc]
144 ldr \rd, [\r_car_base, #\pll_misc]
155 ldr \rd, [\r_car_base, #\pll_base]
162 ldr \rd, [\car, #\iddq]
168 ldr \rd, [\car, #\iddq]
233 ldr r3, [r1] @ read CSR
252 ldr r0, [r2]
386 ldr r1, [r7]
428 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
437 ldr r1, [r7]
443 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
446 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
454 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
471 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
473 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
475 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
479 ldr r1, [r0, #EMC_CFG_DIG_DLL]
490 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
496 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
500 ldr r1, [r0, #EMC_CFG]
514 ldr r2, [r0, #EMC_EMC_STATUS]
521 ldr r2, [r0, #EMC_FBIO_CFG5]
530 ldr r2, [r7]
540 ldr r2, [r7]
549 ldr r2, [r7]
559 ldr r2, [r7]
566 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
568 ldr r1, [r5, #0x0] @ restore EMC_CFG
584 ldr r0, [r0, #PMC_SCRATCH41]
672 ldr r1, [r7]
681 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
686 ldr r1, [r7]
699 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
706 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
714 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
717 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
720 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
751 ldr r0, [r6, r2]
765 ldr r0, [r6, r2] /* memory barrier */
805 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
807 ldr r1, [r0]
829 ldr r1, [r0, #EMC_CFG]
836 ldr r1, [r7]
841 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
849 ldr r1, [r0, #EMC_EMC_STATUS]
859 ldr r2, [r0, #EMC_EMC_STATUS]
865 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
869 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
886 ldr r1, [r4, #PMC_CTRL]