Lines Matching full:r1
207 cpu_to_csr_reg r1, r3
208 add r1, r1, r12 @ virtual CSR address for this CPU
225 str r12, [r1]
233 ldr r3, [r1] @ read CSR
234 str r3, [r1] @ clear CSR
306 mov32 r1, tegra30_iram_start
307 sub r0, r0, r1
308 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
309 add r0, r0, r1
370 mov r1, #(1 << 28)
371 str r1, [r0, #CLK_RESET_SCLK_BURST]
372 str r1, [r0, #CLK_RESET_CCLK_BURST]
373 mov r1, #0
374 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
375 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
381 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
382 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
383 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
386 ldr r1, [r7]
387 add r1, r1, #2
388 wait_until r1, r7, r3
392 pllm_pmc_enable r1, r2
394 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
395 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
396 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
403 pllm_pmc_enable r1, r2
405 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
406 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
409 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
410 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
412 pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
413 pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
414 pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
415 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
422 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
423 cmp r1, #TEGRA30
426 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
428 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
429 bic r1, r1, #(1<<31) @ disable PllP bypass
430 str r1, [r0, #CLK_RESET_PLLP_BASE]
432 mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
433 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
437 ldr r1, [r7]
438 add r1, r1, #LOCK_DELAY
439 wait_until r1, r7, r3
454 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
455 mvn r1, r1
456 bic r1, r1, #(1 << 31)
457 orr r1, r1, #(1 << 30)
458 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
471 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
472 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
473 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
474 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
475 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
476 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
479 ldr r1, [r0, #EMC_CFG_DIG_DLL]
480 orr r1, r1, #(1 << 30) @ set DLL_RESET
481 str r1, [r0, #EMC_CFG_DIG_DLL]
483 emc_timing_update r1, r0
486 movweq r1, #:lower16:TEGRA_EMC1_BASE
487 movteq r1, #:upper16:TEGRA_EMC1_BASE
488 cmpeq r0, r1
490 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
491 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
492 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
493 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
496 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
497 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
500 ldr r1, [r0, #EMC_CFG]
501 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
502 str r1, [r0, #EMC_CFG]
504 mov r1, #0
505 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
506 mov r1, #1
508 streq r1, [r0, #EMC_NOP]
509 streq r1, [r0, #EMC_NOP]
511 emc_device_mask r1, r0
515 ands r2, r2, r1
518 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
534 tst r1, #2
553 tst r1, #2
564 mov r1, #0 @ unstall all transactions
565 str r1, [r0, #EMC_REQ_CTRL]
566 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
567 str r1, [r0, #EMC_ZCAL_INTERVAL]
568 ldr r1, [r5, #0x0] @ restore EMC_CFG
569 str r1, [r0, #EMC_CFG]
571 emc_timing_update r1, r0
576 mov32 r1, TEGRA_EMC1_BASE
577 cmp r0, r1
578 movne r0, r1
672 ldr r1, [r7]
673 add r1, r1, #2
674 wait_until r1, r7, r9
686 ldr r1, [r7]
687 add r1, r1, #2
688 wait_until r1, r7, r9
691 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
692 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
693 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
694 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
695 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
696 store_pllm_pmc_state r0, r1, r4
704 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
705 cmp r1, #TEGRA30
726 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
748 cpu_id r1
750 cpu_to_csr_reg r2, r1
762 cpu_to_halt_reg r2, r1
807 ldr r1, [r0]
808 str r1, [r8, r9] @ save the content of the addr
826 mov r1, #0
827 str r1, [r0, #EMC_ZCAL_INTERVAL]
828 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
829 ldr r1, [r0, #EMC_CFG]
830 bic r1, r1, #(1 << 28)
831 bicne r1, r1, #(1 << 29)
832 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
834 emc_timing_update r1, r0
836 ldr r1, [r7]
837 add r1, r1, #5
838 wait_until r1, r7, r2
841 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
842 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
845 mov r1, #3
846 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
849 ldr r1, [r0, #EMC_EMC_STATUS]
850 tst r1, #4
853 mov r1, #1
854 str r1, [r0, #EMC_SELF_REF]
856 emc_device_mask r1, r0
860 and r2, r2, r1
861 cmp r2, r1
865 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
867 and r1, r1, r2
868 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
869 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
871 orreq r1, r1, #7 @ set E_NO_VTTGEN
872 orrne r1, r1, #0x3f
873 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
875 emc_timing_update r1, r0
880 mov32 r1, TEGRA_EMC1_BASE
881 cmp r0, r1
882 movne r0, r1
886 ldr r1, [r4, #PMC_CTRL]
887 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
893 mov32 r1, 0x8EC00000
894 str r1, [r4, #PMC_IO_DPD_REQ]