Lines Matching full:r0
182 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
191 * and powergates it -- flags (in R0) indicate the request type.
194 * corrupts r0-r4, r10-r12
236 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
252 ldr r0, [r2]
283 mov r4, r0
285 mov r0, #TEGRA_FLUSH_CACHE_ALL
287 mov r0, r4
303 add r3, r3, r0
305 mov32 r0, tegra30_tear_down_core
307 sub r0, r0, r1
309 add r0, r0, r1
323 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
327 mov r0, #0 @ power mode flags (!hotplug)
329 mov r0, #1 @ never return here
368 mov32 r0, TEGRA_CLK_RESET_BASE
371 str r1, [r0, #CLK_RESET_SCLK_BURST]
372 str r1, [r0, #CLK_RESET_CCLK_BURST]
374 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
375 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
381 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
382 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
383 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
394 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
395 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
396 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
405 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
406 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
409 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
410 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
412 pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
413 pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
414 pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
415 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
426 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
428 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
430 str r1, [r0, #CLK_RESET_PLLP_BASE]
433 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
444 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
447 str r4, [r0, #CLK_RESET_SCLK_BURST]
451 str r4, [r0, #CLK_RESET_CCLK_BURST]
461 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
462 movteq r0, #:upper16:TEGRA_EMC_BASE
464 movweq r0, #:lower16:TEGRA_EMC0_BASE
465 movteq r0, #:upper16:TEGRA_EMC0_BASE
467 movweq r0, #:lower16:TEGRA124_EMC_BASE
468 movteq r0, #:upper16:TEGRA124_EMC_BASE
472 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
474 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
476 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
479 ldr r1, [r0, #EMC_CFG_DIG_DLL]
481 str r1, [r0, #EMC_CFG_DIG_DLL]
483 emc_timing_update r1, r0
488 cmpeq r0, r1
490 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
493 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
496 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
500 ldr r1, [r0, #EMC_CFG]
502 str r1, [r0, #EMC_CFG]
505 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
508 streq r1, [r0, #EMC_NOP]
509 streq r1, [r0, #EMC_NOP]
511 emc_device_mask r1, r0
514 ldr r2, [r0, #EMC_EMC_STATUS]
521 ldr r2, [r0, #EMC_FBIO_CFG5]
529 str r2, [r0, #EMC_ZQ_CAL]
539 str r2, [r0, #EMC_ZQ_CAL]
548 str r2, [r0, #EMC_MRW]
558 str r2, [r0, #EMC_MRW]
565 str r1, [r0, #EMC_REQ_CTRL]
567 str r1, [r0, #EMC_ZCAL_INTERVAL]
569 str r1, [r0, #EMC_CFG]
571 emc_timing_update r1, r0
577 cmp r0, r1
578 movne r0, r1
583 mov32 r0, TEGRA_PMC_BASE
584 ldr r0, [r0, #PMC_SCRATCH41]
585 ret r0 @ jump to tegra_resume
669 mov r0, #(1 << 28)
670 str r0, [r5, #CLK_RESET_SCLK_BURST]
675 str r0, [r5, #CLK_RESET_CCLK_BURST]
676 mov r0, #0
677 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
678 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
681 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
682 orr r0, r0, #MSELECT_CLKM
683 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
691 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
692 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
693 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
694 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
695 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
696 store_pllm_pmc_state r0, r1, r4
699 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
700 bic r0, r0, #(1 << 12)
701 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
706 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
707 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
708 bic r0, r0, #(1 << 30)
709 str r0, [r5, #CLK_RESET_PLLP_BASE]
711 mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
712 str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
714 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
715 bic r0, r0, #(1 << 30)
716 str r0, [r5, #CLK_RESET_PLLA_BASE]
717 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
718 bic r0, r0, #(1 << 30)
719 str r0, [r5, #CLK_RESET_PLLC_BASE]
720 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
721 bic r0, r0, #(1 << 30)
722 str r0, [r5, #CLK_RESET_PLLX_BASE]
734 mov r0, #(1 << 24)
735 str r0, [r5, #CLK_RESET_SCLK_BURST]
751 ldr r0, [r6, r2]
752 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
753 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
754 str r0, [r6, r2]
758 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
759 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
760 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
763 str r0, [r6, r2]
765 ldr r0, [r6, r2] /* memory barrier */
805 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
807 ldr r1, [r0]
818 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
820 ldreq r0, =TEGRA_EMC0_BASE
822 ldreq r0, =TEGRA124_EMC_BASE
827 str r1, [r0, #EMC_ZCAL_INTERVAL]
828 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
829 ldr r1, [r0, #EMC_CFG]
832 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
834 emc_timing_update r1, r0
841 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
846 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
849 ldr r1, [r0, #EMC_EMC_STATUS]
854 str r1, [r0, #EMC_SELF_REF]
856 emc_device_mask r1, r0
859 ldr r2, [r0, #EMC_EMC_STATUS]
865 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
868 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
869 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
873 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
875 emc_timing_update r1, r0
881 cmp r0, r1
882 movne r0, r1