Lines Matching refs:ldr
51 ldr \rd, tegra_pll_state
56 ldr \rd, [\r_car_base, #\pll_base]
58 ldr \rd, tegra_pll_state
69 ldr \rd, [\r_car_base, #\pll_base]
77 ldr \rd, [\base, #EMC_ADR_CFG]
115 ldr r3, =TEGRA_FLOW_CTRL_VIRT
118 ldr r2, [r3, r1]
123 ldr r3, =TEGRA_CLK_RESET_VIRT
211 ldr r6, tegra20_sdram_pad_size
213 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
215 ldr r1, [r4, r5]
225 ldr r1, [r7]
230 ldr r4, [r4]
236 ldr r1, [r0, #EMC_CFG]
249 ldr r2, [r0, #EMC_EMC_STATUS]
257 ldr r0, [r0, #PMC_SCRATCH41]
292 ldr r1, [r7]
301 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
304 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
307 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
333 ldr r0, [r6, r1] /* memory barrier */
355 ldr r2, [r1, #EMC_EMC_STATUS]
365 ldr r3, [r1, #EMC_EMC_STATUS]
375 ldr r6, tegra20_sdram_pad_size
377 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
379 ldr r1, [r0]
382 ldr r1, [r3, r5]
391 ldr r0, [r5, #CLK_RESET_SCLK_BURST]