Lines Matching full:r0
92 cpu_id r0
100 * r0 is cpu to reset
108 * corrupts r0-r3, r12
111 cmp r0, #0
114 cpu_to_halt_reg r1, r0
122 mov r1, r1, lsl r0
128 cmp r3, r0
142 mov r4, r0
144 mov r0, #TEGRA_FLUSH_CACHE_ALL
146 mov r0, r4
149 add r3, r3, r0
151 mov32 r0, tegra20_tear_down_core
153 sub r0, r0, r1
155 add r0, r0, r1
194 mov32 r0, TEGRA_CLK_RESET_BASE
197 str r1, [r0, #CLK_RESET_SCLK_BURST]
198 str r1, [r0, #CLK_RESET_CCLK_BURST]
200 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
201 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
203 pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
204 pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
205 pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
231 str r4, [r0, #CLK_RESET_SCLK_BURST]
233 str r4, [r0, #CLK_RESET_CCLK_BURST]
235 mov32 r0, TEGRA_EMC_BASE
236 ldr r1, [r0, #EMC_CFG]
238 str r1, [r0, #EMC_CFG]
241 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
243 str r1, [r0, #EMC_NOP]
244 str r1, [r0, #EMC_NOP]
246 emc_device_mask r1, r0
249 ldr r2, [r0, #EMC_EMC_STATUS]
254 str r1, [r0, #EMC_REQ_CTRL]
256 mov32 r0, TEGRA_PMC_BASE
257 ldr r0, [r0, #PMC_SCRATCH41]
258 ret r0 @ jump to tegra_resume
283 mov r0, #(1 << 28)
284 str r0, [r5, #CLK_RESET_SCLK_BURST]
285 str r0, [r5, #CLK_RESET_CCLK_BURST]
286 mov r0, #0
287 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
288 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
296 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
297 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
298 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
301 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
302 bic r0, r0, #(1 << 30)
303 str r0, [r5, #CLK_RESET_PLLM_BASE]
304 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
305 bic r0, r0, #(1 << 30)
306 str r0, [r5, #CLK_RESET_PLLP_BASE]
307 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
308 bic r0, r0, #(1 << 30)
309 str r0, [r5, #CLK_RESET_PLLC_BASE]
312 mov r0, #0 /* brust policy = 32KHz */
313 str r0, [r5, #CLK_RESET_SCLK_BURST]
327 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
328 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
331 str r0, [r6, r1]
333 ldr r0, [r6, r1] /* memory barrier */
377 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
379 ldr r1, [r0]
383 str r1, [r0] @ set the save val to the addr
391 ldr r0, [r5, #CLK_RESET_SCLK_BURST]
393 str r0, [r2]