Lines Matching +full:0 +full:x8c8
23 #define EMC_CFG 0xc
24 #define EMC_ADR_CFG 0x10
25 #define EMC_NOP 0xdc
26 #define EMC_SELF_REF 0xe0
27 #define EMC_REQ_CTRL 0x2b0
28 #define EMC_EMC_STATUS 0x2b4
30 #define CLK_RESET_CCLK_BURST 0x20
31 #define CLK_RESET_CCLK_DIVIDER 0x24
32 #define CLK_RESET_SCLK_BURST 0x28
33 #define CLK_RESET_SCLK_DIVIDER 0x2c
34 #define CLK_RESET_PLLC_BASE 0x80
35 #define CLK_RESET_PLLM_BASE 0x90
36 #define CLK_RESET_PLLP_BASE 0xa0
38 #define APB_MISC_XM2CFGCPADCTRL 0x8c8
39 #define APB_MISC_XM2CFGDPADCTRL 0x8cc
40 #define APB_MISC_XM2CLKCFGPADCTRL 0x8d0
41 #define APB_MISC_XM2COMPPADCTRL 0x8d4
42 #define APB_MISC_XM2VTTGENPADCTRL 0x8d8
43 #define APB_MISC_XM2CFGCPADCTRL2 0x8e4
44 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8
46 #define PLLC_STORE_MASK (1 << 0)
78 tst \rd, #(0x3 << 24)
79 moveq \rd, #(0x1 << 8) @ just 1 device
80 movne \rd, #(0x3 << 8) @ 2 devices
106 * MUST NOT BE CALLED FOR CPU 0.
111 cmp r0, #0
112 reteq lr @ must not be called for CPU 0
121 movw r1, 0x1011
124 str r1, [r3, #0x340] @ put slave CPU in reset
199 mov r1, #0
209 mov r5, #0
226 add r1, r1, #0xff
240 mov r1, #0
253 mov r1, #0 @ unstall all transactions
286 mov r0, #0
312 mov r0, #0 /* brust policy = 32KHz */
373 mov r5, #0
410 .word 0x8
411 .word 0x8
412 .word 0x0
413 .word 0x8
414 .word 0x5500
415 .word 0x08080040
416 .word 0x0
419 .word 0x0
423 .long 0
427 .word 0x0