Lines Matching +full:0 +full:x78000000

22 	if (bus->number != 0 || (devfn >> 3) != 0)  in nanoengine_pci_map_bus()
42 DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
62 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
63 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
64 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
65 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
66 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
71 pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
72 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
73 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
74 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
75 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
76 pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
77 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
88 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
89 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
90 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
91 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
92 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
97 pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
98 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
99 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
100 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
101 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
102 pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
103 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
109 Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
110 Interrupt: pin A routed to IRQ 0
111 Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
116 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
117 Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
124 .start = 0x78000000,
125 .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
157 int ret = 0; in pci_nanoengine_setup()
159 pcibios_min_io = 0; in pci_nanoengine_setup()
160 pcibios_min_mem = 0; in pci_nanoengine_setup()
162 if (nr == 0) { in pci_nanoengine_setup()
164 sys->io_offset = 0x400; in pci_nanoengine_setup()
188 return 0; in nanoengine_pci_init()