Lines Matching full:write
14 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
15 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
17 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
18 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
19 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
22 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
23 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
24 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
25 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
30 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
31 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
33 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
34 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
35 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
38 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
39 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
40 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
41 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
46 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
47 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
49 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
50 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
51 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
54 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
55 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
56 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
57 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
62 #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
63 #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
65 #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
66 #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
67 #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
70 #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
71 #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
73 #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
75 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
76 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */