1 // SPDX-License-Identifier: GPL-2.0-only
8  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
17  * to the Cortex-A9 processor must be asserted by the external
24  *	----------------------------------------------
30  *	----------------------------------------------
33  * and first to wake-up when MPUSS low power states are excercised
47 #include <asm/hardware/cache-l2x0.h>
49 #include "soc.h"
52 #include "omap4-sar-layout.h"
59 #include "prm-regbits-44xx.h"
74  * struct cpu_pm_ops - CPU pm operations
121 	if (pm_info->wkup_sar_addr)  in set_cpu_wakeup_addr()
122 		writel_relaxed(addr, pm_info->wkup_sar_addr);  in set_cpu_wakeup_addr()
147 	if (pm_info->scu_sar_addr)  in scu_pwrst_prepare()
148 		writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);  in scu_pwrst_prepare()
186 	if (pm_info->l2x0_sar_addr)  in l2x0_pwrst_prepare()
187 		writel_relaxed(save_state, pm_info->l2x0_sar_addr);  in l2x0_pwrst_prepare()
220  *	0 - Nothing lost and no need to save: MPUSS INACTIVE
221  *	1 - CPUx L1 and logic lost: MPUSS CSWR
222  *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
223  *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
231 		return -ENXIO;  in omap4_enter_lowpower()
254 		return -ENXIO;  in omap4_enter_lowpower()
269 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);  in omap4_enter_lowpower()
270 	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);  in omap4_enter_lowpower()
276 	 * Call low level function  with targeted low power state.  in omap4_enter_lowpower()
293 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_enter_lowpower()
311 		return -ENXIO;  in omap4_hotplug_cpu()
314 	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,  in omap4_hotplug_cpu()
320 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_hotplug_cpu()
321 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);  in omap4_hotplug_cpu()
332 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_hotplug_cpu()
360 		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");  in omap4_mpuss_init()
361 		return -ENODEV;  in omap4_mpuss_init()
367 		pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;  in omap4_mpuss_init()
369 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
372 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
374 		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;  in omap4_mpuss_init()
376 	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");  in omap4_mpuss_init()
377 	if (!pm_info->pwrdm) {  in omap4_mpuss_init()
379 		return -ENODEV;  in omap4_mpuss_init()
383 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_mpuss_init()
387 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_mpuss_init()
391 		pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;  in omap4_mpuss_init()
393 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
396 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
398 		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;  in omap4_mpuss_init()
401 	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");  in omap4_mpuss_init()
402 	if (!pm_info->pwrdm) {  in omap4_mpuss_init()
404 		return -ENODEV;  in omap4_mpuss_init()
408 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_mpuss_init()
412 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_mpuss_init()
417 		return -ENODEV;  in omap4_mpuss_init()
423 		/* Save device type on scratchpad for low level code to use */  in omap4_mpuss_init()