Lines Matching +full:0 +full:xff00

72 	mov	r4, #0
73 mcr p15, 0, r0, c7, c10, 4
77 mov r6, #TCMIF_ASM_BASE & 0xff000000
78 orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
79 orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
82 ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
83 orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
84 orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
85 str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
89 orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
90 str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
93 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
94 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
95 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
98 @ do not disable PERCK (0x04)
99 mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
100 orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
101 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
104 mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
105 orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
106 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
109 mrc p15, 0, r9, c1, c0, 0
110 bic r2, r9, #0x1000
111 mcr p15, 0, r2, c1, c0, 0
118 mov r2, #0
119 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
127 mcr p15, 0, r9, c1, c0, 0
130 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
131 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
134 str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
135 str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
152 mov r4, #TCMIF_ASM_BASE & 0xff000000
153 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
154 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
158 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
159 bic r5, r5, #PDE_BIT & 0xff
160 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
163 and r5, r5, #PWD_EN_BIT & 0xff
164 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
167 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
168 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
169 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
170 str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
173 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
174 orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
175 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
178 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
179 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
180 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
183 mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
184 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
185 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
188 mov r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
189 orr r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
190 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
192 mov r5, #IDLE_WAIT_CYCLES & 0xff
193 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
201 mov r2, #0
202 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
209 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
210 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
227 mov r4, #0
228 mcr p15, 0, r0, c7, c10, 4
232 mov r6, #TCMIF_ASM_BASE & 0xff000000
233 orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
234 orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
237 ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
238 orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
239 orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
240 str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
243 ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
244 orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
245 str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
248 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
249 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
250 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
253 @ Do not disable PERCK (0x04)
254 mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
255 orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
256 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
259 mov r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
260 orr r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
261 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
267 mov r2, #0
268 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
358 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
359 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
362 str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
363 str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]