Lines Matching +full:no +full:- +full:idle +full:- +full:on +full:- +full:init
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock_data.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
18 #include <linux/clk-provider.h>
21 #include <linux/soc/ti/omap1-io.h>
23 #include <asm/mach-types.h> /* for machine_is_* */
32 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
43 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
50 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
53 /* Some OTG_SYSCON_2-specific bit fields */
56 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
77 .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
82 .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
91 * FIXME: This clock seems to be necessary but no-one has asked for its
96 .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
106 .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
117 .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
126 .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
141 * FIXME: This clock seems to be necessary but no-one has asked for its
145 .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
153 .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
165 .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
177 .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
189 .hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0),
190 /* Note: On 16xx the frequency can be divided by 2 by programming
198 .hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
209 .hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
217 .hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
228 .hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0),
235 .hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0),
243 .hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
254 .hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0),
255 /* Note: On 1510 the frequency follows TC_CK
262 /* No-idle controlled by "tc_ck" */
263 .hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0),
267 /* No-idle controlled by "tc_ck" */
268 .hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0),
275 .hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0),
282 * FIXME: This clock seems to be necessary but no-one has asked for its
287 .hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
294 /* No-idle controlled by "tc_ck" */
295 .hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0),
299 .hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0),
304 .hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0),
315 .hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0),
325 .hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0),
329 .hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0),
333 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
345 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
360 * XXX The enable_bit here is misused - it simply switches between 12MHz
366 /* Direct from ULPD, no real parent */
367 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
377 * XXX The enable_bit here is misused - it simply switches between 12MHz
385 /* Direct from ULPD, no real parent */
386 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
396 * XXX The enable_bit here is misused - it simply switches between 12MHz
402 /* Direct from ULPD, no real parent */
403 .hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0),
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
419 /* Direct from ULPD, no real parent */
420 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
430 * XXX The enable_bit here is misused - it simply switches between 12MHz
438 /* Direct from ULPD, no real parent */
439 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
448 static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
450 /* Direct from ULPD, no parent */
451 .hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0),
460 /* Direct from ULPD, no parent */
461 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
470 /* Direct from ULPD, no parent */
471 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
473 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
481 /* Direct from ULPD, no parent */
482 .hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0),
490 /* Direct from ULPD, no parent */
491 .hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0),
499 /* Direct from ULPD, no parent */
500 .hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0),
508 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
509 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
517 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
518 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
523 .init = &omap1_init_ext_clk,
527 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
528 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0),
534 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
535 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0),
540 .init = &omap1_init_ext_clk,
546 .hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0),
560 .hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0),
570 .hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0),
579 .hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0),
586 remains active during MPU idle whenever this is enabled */
588 .hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0),
593 .hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0),
602 /* non-ULPD clocks */
654 CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
656 CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
657 CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
658 CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
669 CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
670 CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
671 CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
672 CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
673 CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
674 CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
675 CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
676 CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
677 CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
681 * init
713 /* By default all idlect1 clocks are allowed to idle */ in omap1_clk_init()
787 /* (on 730, bit 13 must not be cleared) */ in omap1_clk_init()
800 * of the ARM_IDLECT2 register must be set to zero. The power-on in omap1_clk_init()
806 if (!(c->cpu & cpu_mask)) in omap1_clk_init()
809 if (c->lk.clk_hw->init) { /* NULL if provider already registered */ in omap1_clk_init()
810 const struct clk_init_data *init = c->lk.clk_hw->init; in omap1_clk_init() local
811 const char *name = c->lk.clk_hw->init->name; in omap1_clk_init()
814 err = clk_hw_register(NULL, c->lk.clk_hw); in omap1_clk_init()
817 /* may be tried again, restore init data */ in omap1_clk_init()
818 c->lk.clk_hw->init = init; in omap1_clk_init()
823 clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id); in omap1_clk_init()