Lines Matching +full:0 +full:xd4207000

9 #define PXA168_U2O_REGBASE	(0xd4208000)
10 #define PXA168_U2O_PHYBASE	(0xd4207000)
12 #define PXA168_U2H_REGBASE      (0xd4209000)
13 #define PXA168_U2H_PHYBASE      (0xd4206000)
15 #define MMP3_HSIC1_REGBASE	(0xf0001000)
16 #define MMP3_HSIC1_PHYBASE	(0xf0001800)
18 #define MMP3_HSIC2_REGBASE	(0xf0002000)
19 #define MMP3_HSIC2_PHYBASE	(0xf0002800)
21 #define MMP3_FSIC_REGBASE	(0xf0003000)
22 #define MMP3_FSIC_PHYBASE	(0xf0003800)
25 #define USB_REG_RANGE		(0x1ff)
26 #define USB_PHY_RANGE		(0xff)
29 #define U2x_CAPREGS_OFFSET       0x100
32 #define UTMI_REVISION		0x0
33 #define UTMI_CTRL		0x4
34 #define UTMI_PLL		0x8
35 #define UTMI_TX			0xc
36 #define UTMI_RX			0x10
37 #define UTMI_IVREF		0x14
38 #define UTMI_T0			0x18
39 #define UTMI_T1			0x1c
40 #define UTMI_T2			0x20
41 #define UTMI_T3			0x24
42 #define UTMI_T4			0x28
43 #define UTMI_T5			0x2c
44 #define UTMI_RESERVE		0x30
45 #define UTMI_USB_INT		0x34
46 #define UTMI_DBG_CTL		0x38
47 #define UTMI_OTG_ADDON		0x3c
62 #define UTMI_CTRL_PWR_UP_SHIFT                  0
66 #define UTMI_PLL_PLLCALI12_MASK			(0x3 << 29)
69 #define UTMI_PLL_PLLVDD18_MASK			(0x3 << 27)
72 #define UTMI_PLL_PLLVDD12_MASK			(0x3 << 25)
75 #define CLK_BLK_EN                              (0x1 << 24)
76 #define PLL_READY                               (0x1 << 23)
77 #define KVCO_EXT                                (0x1 << 22)
78 #define VCOCAL_START                            (0x1 << 21)
81 #define UTMI_PLL_KVCO_MASK                      (0x7 << 15)
84 #define UTMI_PLL_ICP_MASK                       (0x7 << 12)
87 #define UTMI_PLL_FBDIV_MASK                     (0xFF << 4)
89 #define UTMI_PLL_REFDIV_SHIFT                   0
90 #define UTMI_PLL_REFDIV_MASK                    (0xF << 0)
94 #define UTMI_TX_REG_EXT_FS_RCAL_MASK		(0xf << 27)
97 #define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK		(0x1 << 26)
100 #define UTMI_TX_TXVDD12_MASK                    (0x3 << 22)
103 #define UTMI_TX_CK60_PHSEL_MASK                 (0xf << 17)
106 #define UTMI_TX_IMPCAL_VTH_MASK                 (0x7 << 14)
108 #define REG_RCAL_START                          (0x1 << 12)
112 #define UTMI_TX_AMP_SHIFT			0
113 #define UTMI_TX_AMP_MASK			(0x7 << 0)
117 #define UTMI_REG_SQ_LENGTH_MASK                 (0x3 << 15)
120 #define UTMI_RX_SQ_THRESH_MASK                  (0xf << 4)
122 #define UTMI_OTG_ADDON_OTG_ON			(1 << 0)
125 #define FSIC_MISC			0x4
126 #define FSIC_INT			0x28
127 #define FSIC_CTRL			0x30
130 #define HSIC_PAD_CTRL			0x4
132 #define HSIC_CTRL			0x8
136 #define TEST_GRP_0			0xc
137 #define TEST_GRP_1			0x10
139 #define HSIC_INT			0x14
145 #define HSIC_INT_CORE			(1<<0)
147 #define HSIC_CONFIG			0x18
148 #define USBHSIC_CTRL			0x20
150 #define HSIC_USB_CTRL			0x28
152 #define	HSIC_USB_CLK_PHY		0x0
153 #define HSIC_USB_CLK_PMU		0x1