30 #define CCR				0x0
31 #define BM_CCR_WB_COUNT			(0x7 << 16)
32 #define BM_CCR_RBC_BYPASS_COUNT		(0x3f << 21)
33 #define BM_CCR_RBC_EN			(0x1 << 27)
35 #define CLPCR				0x54
36 #define BP_CLPCR_LPM			0
37 #define BM_CLPCR_LPM			(0x3 << 0)
38 #define BM_CLPCR_BYPASS_PMIC_READY	(0x1 << 2)
39 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
40 #define BM_CLPCR_SBYOS			(0x1 << 6)
41 #define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
42 #define BM_CLPCR_VSTBY			(0x1 << 8)
44 #define BM_CLPCR_STBY_COUNT		(0x3 << 9)
45 #define BM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
46 #define BM_CLPCR_WB_PER_AT_LPM		(0x1 << 16)
47 #define BM_CLPCR_WB_CORE_AT_LPM		(0x1 << 17)
48 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS	(0x1 << 19)
49 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS	(0x1 << 21)
50 #define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
51 #define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
52 #define BM_CLPCR_MASK_CORE2_WFI		(0x1 << 24)
53 #define BM_CLPCR_MASK_CORE3_WFI		(0x1 << 25)
54 #define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 26)
55 #define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 27)
57 #define CGPR				0x64
58 #define BM_CGPR_INT_MEM_CLK_LPM		(0x1 << 17)
60 #define MX6Q_SUSPEND_OCRAM_SIZE		0x1000
98 	0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
99 	0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
100 	0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
101 	0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
102 	0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
103 	0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
104 	0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
105 	0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
106 	0x74c,			    /* GPR_ADDS */
110 	0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
111 	0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
112 	0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
113 	0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
114 	0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
115 	0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
116 	0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
117 	0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
118 	0x74c,			    /* GPR_ADDS */
122 	0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
123 	0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
124 	0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
125 	0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
126 	0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
130 	0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
131 	0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
132 	0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
133 	0x2a4, 0x2a8,		    /* SDCKE0, SDCKE1*/
137 	0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
138 	0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
139 	0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
140 	0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
141 	0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
145 	0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
146 	0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
147 	0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
148 	0x494, 0x4b0,	            /* MODE_CTL, MODE, */
256 	val |= enable ? BM_CCR_RBC_EN : 0;  in imx6_enable_rbc()
262 	val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;  in imx6_enable_rbc()
283 	val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;  in imx6q_enable_wb()
289 	val |= enable ? BM_CCR_WB_COUNT : 0;  in imx6q_enable_wb()
302 		val |= 0x1 << BP_CLPCR_LPM;  in imx6_set_lpm()
306 		val |= 0x2 << BP_CLPCR_LPM;  in imx6_set_lpm()
318 		val |= 0x1 << BP_CLPCR_LPM;  in imx6_set_lpm()
323 		val |= 0x2 << BP_CLPCR_LPM;  in imx6_set_lpm()
324 		val |= 0x3 << BP_CLPCR_STBY_COUNT;  in imx6_set_lpm()
349 	 *    is set (set bits 0-1 of CCM_CLPCR).  in imx6_set_lpm()
351 	 * Note that IRQ #32 is GIC SPI #0.  in imx6_set_lpm()
354 		imx_gpc_hwirq_unmask(0);  in imx6_set_lpm()
357 		imx_gpc_hwirq_mask(0);  in imx6_set_lpm()
359 	return 0;  in imx6_set_lpm()
379 	return 0;  in imx6q_suspend_finish()
411 		cpu_suspend(0, imx6q_suspend_finish);  in imx6q_pm_enter()
425 	return 0;  in imx6q_pm_enter()
443 	int ret = 0;  in imx6_pm_get_base()
449 	ret = of_address_to_resource(node, 0, &res);  in imx6_pm_get_base()
471 	int i, ret = 0;  in imx6q_suspend_init()
513 	memset(suspend_ocram_base, 0, sizeof(*pm_info));  in imx6q_suspend_init()
562 	for (i = 0; i < pm_info->mmdc_io_num; i++) {  in imx6q_suspend_init()
563 		pm_info->mmdc_io_val[i][0] =  in imx6q_suspend_init()
625 	gic_cpu_if_down(0);  in imx6_pm_stby_poweroff()
627 	imx6q_suspend_finish(0);  in imx6_pm_stby_poweroff()
643 	return 0;  in imx6_pm_stby_poweroff_probe()
652 	ccm_base = of_iomap(np, 0);  in imx6_pm_ccm_init()
690 				IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);  in imx6sl_pm_init()