Lines Matching +full:0 +full:x53fd4000
25 #define MXC_CCM_CLPCR 0x54
26 #define MXC_CCM_CLPCR_LPM_OFFSET 0
27 #define MXC_CCM_CLPCR_LPM_MASK 0x3
29 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
30 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
32 #define MXC_CORTEXA8_PLAT_LPC 0xc
33 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
36 #define MXC_SRPG_NEON_SRPGCR 0x280
37 #define MXC_SRPG_ARM_SRPGCR 0x2a0
38 #define MXC_SRPG_EMPGC0_SRPGCR 0x2c0
39 #define MXC_SRPG_EMPGC1_SRPGCR 0x2d0
73 #define MX53_DSE_HIGHZ_MASK (0x7 << 19)
74 {.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */
75 {.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */
76 {.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */
77 {.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */
78 {.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
79 {.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
80 {.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */
81 {.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */
83 {.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */
84 {.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */
85 {.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */
86 {.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */
87 {.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */
88 {.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */
89 {.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */
90 {.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */
91 {.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */
92 {.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */
93 {.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */
96 {.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */
100 .ccm_addr = 0x73fd4000,
101 .cortex_addr = 0x83fa0000,
102 .gpc_addr = 0x73fd8000,
106 .ccm_addr = 0x53fd4000,
107 .cortex_addr = 0x63fa0000,
108 .gpc_addr = 0x53fd8000,
109 .m4if_addr = 0x63fd8000,
110 .iomuxc_addr = 0x53fa8000,
147 int stop_mode = 0; in mx5_cpu_lp_set()
165 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
172 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
175 stop_mode = 0; in mx5_cpu_lp_set()
177 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
178 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; in mx5_cpu_lp_set()
186 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
225 imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_suspend_enter()
226 imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_suspend_enter()
239 return 0; in mx5_suspend_enter()
278 int ret = 0; in imx_suspend_alloc_ocram()
331 return 0; in imx5_suspend_init()
365 return 0; in imx5_suspend_init()
407 return 0; in imx5_pm_common_init()