Lines Matching full:divide
595 * These four bits set the divide ratio between the PLL2 in ep93xx_clock_init()
597 * 0000 - Divide by 1 in ep93xx_clock_init()
598 * 0001 - Divide by 2 in ep93xx_clock_init()
599 * 0010 - Divide by 3 in ep93xx_clock_init()
600 * 0011 - Divide by 4 in ep93xx_clock_init()
601 * 0100 - Divide by 5 in ep93xx_clock_init()
602 * 0101 - Divide by 6 in ep93xx_clock_init()
603 * 0110 - Divide by 7 in ep93xx_clock_init()
604 * 0111 - Divide by 8 in ep93xx_clock_init()
605 * 1000 - Divide by 9 in ep93xx_clock_init()
606 * 1001 - Divide by 10 in ep93xx_clock_init()
607 * 1010 - Divide by 11 in ep93xx_clock_init()
608 * 1011 - Divide by 12 in ep93xx_clock_init()
609 * 1100 - Divide by 13 in ep93xx_clock_init()
610 * 1101 - Divide by 14 in ep93xx_clock_init()
611 * 1110 - Divide by 15 in ep93xx_clock_init()
612 * 1111 - Divide by 1 in ep93xx_clock_init()