Lines Matching +full:0 +full:x01c00000
37 #define DM365_RTC_BASE 0x01c69000
38 #define DM365_KEYSCAN_BASE 0x01c69400
39 #define DM365_OSD_BASE 0x01c71c00
40 #define DM365_VENC_BASE 0x01c71e00
41 #define DAVINCI_DM365_VC_BASE 0x01d0c000
44 #define DM365_EMAC_BASE 0x01d07000
45 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
46 #define DM365_EMAC_CNTRL_OFFSET 0x0000
47 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
48 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
49 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
51 #define INTMUX 0x18
52 #define EVTMUX 0x1c
57 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
59 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
69 MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
70 MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
74 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
75 MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
76 MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
78 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
79 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
80 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
81 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
82 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
83 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
114 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
116 MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
118 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
133 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
135 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
143 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
144 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
145 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
146 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
147 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
159 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
160 MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
161 MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
162 MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
163 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
164 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
165 MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
168 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
169 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
170 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
171 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
172 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
173 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
174 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
175 MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
176 MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
188 INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
189 INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
190 INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
191 INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
193 INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
195 INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
197 EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
198 EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
199 EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
215 .start = 0x01c66000,
216 .end = 0x01c667ff,
227 .id = 0,
245 if (chipselect_mask & BIT(0)) in dm365_init_spi0()
305 .base = 0,
373 .id = 0,
448 {0, 7},
451 {3, 0},
456 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
457 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
458 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
459 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
460 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
461 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
462 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
463 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
464 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
465 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
466 { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
467 { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
468 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
469 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
470 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
471 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
484 .start = 0x01c00000,
485 .end = 0x01c00000 + SZ_64K - 1,
490 .start = 0x01c10000,
491 .end = 0x01c10000 + SZ_1K - 1,
496 .start = 0x01c10400,
497 .end = 0x01c10400 + SZ_1K - 1,
502 .start = 0x01c10800,
503 .end = 0x01c10800 + SZ_1K - 1,
508 .start = 0x01c10c00,
509 .end = 0x01c10c00 + SZ_1K - 1,
527 .id = 0,
600 .id = 0,
631 .id = 0,
639 .variant = 0x0,
640 .part_no = 0xb83e,
641 .manufacturer = 0x017,
646 .variant = 0x8,
647 .part_no = 0xb83e,
648 .manufacturer = 0x017,
666 #define DM365_UART1_BASE (IO_PHYS + 0x106000)
678 .flags = 0,
691 .flags = 0,
717 .jtag_id_reg = 0x01c40028,
724 .sram_dma = 0x00010000,
772 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ); in dm365_init_time()
802 .start = 0x01c70000,
803 .end = 0x01c70000 + 0xff,
809 .start = 0x01c70200,
810 .end = 0x01c70200 + 0xff,
860 .start = 0x01c71000,
861 .end = 0x01c71000 + 0x1ff,
864 /* ISIF Linearization table 0 */
866 .start = 0x1C7C000,
867 .end = 0x1C7C000 + 0x2ff,
872 .start = 0x1C7C400,
873 .end = 0x1C7C400 + 0x2ff,
892 .end = DM365_OSD_BASE + 0xff,
919 .end = DM365_VENC_BASE + 0x177,
939 .end = DM365_VENC_BASE + 0x177,
964 return 0; in dm365_vpbe_setup_pinmux()
993 return 0; in dm365_venc_setup_clock()
1052 return 0; in dm365_init_video()
1073 int ret = 0; in dm365_init_devices()
1076 return 0; in dm365_init_devices()