Lines Matching +full:0 +full:x01c70000
37 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
38 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
39 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
50 .start = 0x01c66000,
51 .end = 0x01c667ff,
69 .id = 0,
86 if (chipselect_mask & BIT(0)) in dm355_init_spi0()
98 #define INTMUX 0x18
99 #define EVTMUX 0x1c
109 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
121 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
128 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
129 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
136 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
137 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
138 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
141 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
142 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
143 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
144 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
146 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
147 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
148 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
149 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
150 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
151 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
152 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
225 {0, 3},
231 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
232 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
233 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
234 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
235 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
236 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
237 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
238 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
239 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
240 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
241 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
242 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
243 { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
244 { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
257 .start = 0x01c00000,
258 .end = 0x01c00000 + SZ_64K - 1,
263 .start = 0x01c10000,
264 .end = 0x01c10000 + SZ_1K - 1,
269 .start = 0x01c10400,
270 .end = 0x01c10400 + SZ_1K - 1,
288 .id = 0,
337 .start = 0x01c70800,
338 .end = 0x01c70800 + 0xff,
344 .start = 0x01c70000,
345 .end = 0x01c70000 + 0xf,
376 .start = 0x01c70600,
377 .end = 0x01c70600 + 0x1ff,
406 .end = DM355_OSD_BASE + 0x17f,
431 .end = DM355_VENC_BASE + 0x17f,
451 .end = DM355_VENC_BASE + 0x17f,
475 return 0; in dm355_vpbe_setup_pinmux()
502 return 0; in dm355_venc_setup_clock()
587 .base = 0,
611 .variant = 0x0,
612 .part_no = 0xb73b,
613 .manufacturer = 0x00f,
641 .flags = 0,
654 .flags = 0,
667 .flags = 0,
700 .jtag_id_reg = 0x01c40028,
706 .sram_dma = 0x00010000,
734 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); in dm355_init_time()
793 return 0; in dm355_init_video()
814 int ret = 0; in dm355_init_devices()
817 return 0; in dm355_init_devices()