Lines Matching refs:ldr
38 2: ldr r8, [pmc, #AT91_PMC_SR]
50 1: ldr r7, [pmc, #AT91_PMC_SR]
61 1: ldr r7, [pmc, #AT91_PMC_SR]
95 ldr r7, .sfrbu
97 ldr r9, [r7, #AT91_SFRBU_25LDOCR]
103 ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
126 ldr r2, .sramc_base
127 ldr r3, .sramc_phy_base
128 ldr r7, .pm_mode
133 ldr tmp1, [r2, #UDDRC_PCTRL_0]
137 ldr tmp1, [r2, #UDDRC_PCTRL_1]
141 ldr tmp1, [r2, #UDDRC_PCTRL_2]
145 ldr tmp1, [r2, #UDDRC_PCTRL_3]
149 ldr tmp1, [r2, #UDDRC_PCTRL_4]
155 ldr tmp1, [r2, #UDDRC_PSTAT]
156 ldr tmp2, =UDDRC_PSTAT_ALL_PORTS
161 ldr tmp1, [r2, #UDDRC_PWRCTL]
167 ldr tmp1, [r2, #UDDRC_STAT]
177 ldr tmp1, [r3, DDR3PHY_ACDLLCR]
182 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
186 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
192 ldr tmp1, [r3, #DDR3PHY_DXCCR]
197 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
204 ldr tmp1, [r3, #DDR3PHY_DSGCR]
215 ldr r2, .sramc_base
216 ldr r3, .sramc_phy_base
219 ldr tmp1, [r3, #DDR3PHY_DXCCR]
224 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
231 ldr tmp1, [r3, #DDR3PHY_DSGCR]
236 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
240 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
249 ldr tmp1, [r2, #UDDRC_DFIMISC]
258 ldr tmp1, [r2, #UDDRC_SWSTAT]
269 ldr tmp1, [r3, #DDR3PHY_PGSR]
278 ldr tmp1, [r2, #UDDRC_DFIMISC]
288 ldr tmp1, [r2, #UDDRC_SWSTAT]
293 ldr tmp1, [r2, #UDDRC_PWRCTL]
299 ldr tmp1, [r2, #UDDRC_STAT]
305 ldr tmp1, [r2, #UDDRC_PCTRL_0]
309 ldr tmp1, [r2, #UDDRC_PCTRL_1]
313 ldr tmp1, [r2, #UDDRC_PCTRL_2]
317 ldr tmp1, [r2, #UDDRC_PCTRL_3]
321 ldr tmp1, [r2, #UDDRC_PCTRL_4]
337 ldr r1, .memtype
338 ldr r2, .sramc_base
357 ldr r3, [r2, #AT91_DDRSDRC_MDR]
367 ldr r3, [r2, #AT91_DDRSDRC_LPR]
374 ldr r2, .sramc1_base
378 ldr r3, [r2, #AT91_DDRSDRC_MDR]
388 ldr r3, [r2, #AT91_DDRSDRC_LPR]
402 ldr r3, [r2, #AT91_SDRAMC_LPR]
408 ldr r3, .saved_sam9_lpr
423 ldr r1, .memtype
424 ldr r2, .sramc_base
446 ldr r3, .saved_sam9_mdr
449 ldr r3, .saved_sam9_lpr
453 ldr r2, .sramc1_base
464 ldr r3, .saved_sam9_lpr
472 ldr pmc, .pmc_base
473 ldr tmp2, .pm_mode
474 ldr tmp3, .mckr_offset
481 ldr tmp1, [pmc, tmp3]
492 ldr tmp1, [pmc, #AT91_CKGR_MOR]
498 ldr tmp1, [pmc, #AT91_PMC_SR]
504 ldr tmp1, [pmc, #AT91_CKGR_MOR]
511 2: ldr tmp1, [pmc, #AT91_PMC_SR]
523 ldr tmp3, .mckr_offset
524 ldr tmp1, [pmc, tmp3]
533 ldr tmp1, .saved_osc_status
538 ldr tmp1, [pmc, #AT91_CKGR_MOR]
545 3: ldr tmp1, [pmc, #AT91_PMC_SR]
550 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
564 ldr pmc, .pmc_base
565 ldr tmp2, .mckr_offset
569 ldr tmp1, [pmc, #AT91_PMC_SR]
575 ldr tmp1, [pmc, #AT91_CKGR_MOR]
582 1: ldr tmp1, [pmc, #AT91_PMC_SR]
587 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
596 ldr tmp1, [pmc, #AT91_CKGR_MOR]
603 ldr tmp1, [pmc, tmp2]
611 ldr tmp1, [pmc, #AT91_CKGR_MOR]
624 ldr tmp1, [pmc, #AT91_CKGR_MOR]
633 ldr tmp1, [pmc, tmp2]
640 ldr tmp1, [pmc, #AT91_CKGR_MOR]
649 ldr tmp1, [pmc, tmp2]
657 ldr tmp1, .saved_osc_status
662 ldr tmp1, [pmc, #AT91_CKGR_MOR]
669 4: ldr tmp1, [pmc, #AT91_PMC_SR]
678 ldr tmp1, .pmc_version
684 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT]
690 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
695 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
701 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
707 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
713 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
719 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
724 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
733 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
744 ldr tmp2, .saved_pllar
745 ldr tmp3, .pmc_version
751 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
757 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
761 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
768 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
774 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
785 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
791 3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
806 1: ldr tmp1, [pmc, #AT91_PMC_SR]
819 ldr pmc, .pmc_base
828 ldr tmp2, [pmc, #AT91_PMC_MCR_V2]
875 ldr pmc, .pmc_base
885 ldr tmp2, .saved_mck1
891 ldr tmp2, .saved_mck2
897 ldr tmp2, .saved_mck3
901 ldr tmp2, .saved_mck4
906 ldr tmp3, [pmc, #AT91_PMC_MCR_V2]
928 ldr pmc, .pmc_base
929 ldr tmp2, .mckr_offset
930 ldr tmp3, .pm_mode
933 ldr tmp1, [pmc, tmp2]
956 ldr tmp3, .pm_mode
971 ldr pmc, .pmc_base
978 ldr tmp1, .mckr_offset
979 ldr tmp2, .saved_mckr
990 ldr pmc, .pmc_base
991 ldr tmp2, .mckr_offset
992 ldr tmp1, [pmc, tmp2]
1000 ldr r0, .sfrbu
1005 1: ldr tmp1, [r0, #0x10]
1010 ldr r0, .shdwc
1036 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
1038 ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
1040 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
1042 ldr tmp1, [r0, #PM_DATA_MODE]
1049 ldr tmp1, [r0, #PM_DATA_PMC]
1054 ldr tmp1, [r0, #PM_DATA_RAMC0]
1059 ldr tmp1, [r0, #PM_DATA_RAMC1]
1066 ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
1071 ldr tmp1, [r0, #PM_DATA_SHDWC]
1076 ldr tmp1, [r0, #PM_DATA_SFRBU]
1085 ldr r0, .pm_mode
1096 ldr pmc, .pmc_base