Lines Matching refs:r6
274 ldr r6, =(_end) @ Cover whole kernel
275 sub r6, r6, r5 @ Minimum size of region to map
276 clz r6, r6 @ Region size must be 2^N...
277 rsb r6, r6, #31 @ ...so round up region size
278 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
279 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
296 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
298 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
307 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled
309 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
311 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
321 ldr r6, =(_exiprom) @ ROM end
322 sub r6, r6, r0 @ Minimum size of region to map
323 clz r6, r6 @ Region size must be 2^N...
324 rsb r6, r6, #31 @ ...so round up region size
325 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
326 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
328 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
330 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
344 ldr r6, =(_exiprom) @ ROM end
345 sub r6, r6, #1
346 bic r6, r6, #(PMSAv8_MINALIGN - 1)
349 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
352 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
354 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
358 ldr r6, =KERNEL_END
359 sub r6, r6, #1
360 bic r6, r6, #(PMSAv8_MINALIGN - 1)
363 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
366 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
368 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
372 ldr r6, =KERNEL_START
374 cmp r6, r5
375 movcs r6, r5
377 ldr r6, =KERNEL_START
379 cmp r6, #0
383 sub r6, r6, #1
384 bic r6, r6, #(PMSAv8_MINALIGN - 1)
387 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
390 AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2
392 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
398 ldr r6, =(_exiprom)
399 cmp r5, r6
400 movcc r5, r6
404 mov r6, #0xffffffff
405 bic r6, r6, #(PMSAv8_MINALIGN - 1)
408 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
411 AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3
413 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
418 ldr r6, =KERNEL_END
419 cmp r5, r6
420 movcs r5, r6
422 ldr r6, =KERNEL_START
424 cmp r6, r0
425 movcc r6, r0
427 sub r6, r6, #1
428 bic r6, r6, #(PMSAv8_MINALIGN - 1)
431 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
440 str r6, [r12, #PMSAv8_RLAR_A(0)]
443 mcr p15, 0, r6, c6, c10, 1 @ PRLAR4
457 ldr r6, [r7] @ get secondary_data.mpu_rgn_info
479 ldr r4, [r6, #MPU_RNG_INFO_USED]
481 add r3, r6, #MPU_RNG_INFO_RNGS
493 ldr r6, [r3, #MPU_RGN_DRSR]
496 setup_region r0, r5, r6, PMSAv7_DATA_SIDE
498 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE
509 ldr r4, [r6, #MPU_RNG_INFO_USED]
514 add r3, r6, #MPU_RNG_INFO_RNGS
525 ldr r6, [r3, #MPU_RGN_PRLAR]
528 mcr p15, 0, r6, c6, c3, 1 @ PRLAR