Lines Matching +full:0 +full:x610
14 #define AURORA_SYNC_REG 0x700
15 #define AURORA_RANGE_BASE_ADDR_REG 0x720
16 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
17 #define AURORA_INVAL_RANGE_REG 0x774
18 #define AURORA_CLEAN_RANGE_REG 0x7b4
19 #define AURORA_FLUSH_RANGE_REG 0x7f4
23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
25 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
38 (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
44 #define AURORA_ERR_CNT_REG 0x600
45 #define AURORA_ERR_ATTR_CAP_REG 0x608
46 #define AURORA_ERR_ADDR_CAP_REG 0x60c
47 #define AURORA_ERR_WAY_CAP_REG 0x610
48 #define AURORA_ERR_INJECT_CTL_REG 0x614
49 #define AURORA_ERR_INJECT_MASK_REG 0x618
53 (0x1 << AURORA_ERR_CNT_CLR_OFFSET)
56 (0x7fff << AURORA_ERR_CNT_UE_OFFSET)
57 #define AURORA_ERR_CNT_CE_OFFSET 0
59 (0xffff << AURORA_ERR_CNT_CE_OFFSET)
63 (0x7 << AURORA_ERR_ATTR_SRC_OFF)
66 (0xf << AURORA_ERR_ATTR_TXN_OFF)
69 (0x3 << AURORA_ERR_ATTR_ERR_OFF)
70 #define AURORA_ERR_ATTR_CAP_VALID_OFF 0
72 (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF)
74 #define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0
78 (0xfff << AURORA_ERR_WAY_IDX_OFF)
81 (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET)
83 #define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0
85 #define AURORA_ERR_INJECT_CTL_EN_MASK 0x3
86 #define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2
87 #define AURORA_ERR_INJECT_CTL_EN_ECC 0x1
93 #define AURORA_CTRL_FW 0x100
98 #define AURORA_CACHE_ID 0x100