Lines Matching +full:4 +full:x12
97 vext.8 q1, q1, q1, #4
131 vext.8 q3, q3, q3, #4
203 .align 4
205 .Lrol8_table: .byte 3, 0, 1, 2, 7, 4, 5, 6
216 // r1: 4 data blocks output, o
217 // r2: 4 data blocks input, i
241 vadd.u32 q12, q12, q4 // x12 += counter values 0-3
259 // x0 += x4, x12 = rotl32(x12 ^ x0, 16)
278 // x8 += x12, x4 = rotl32(x4 ^ x8, 12)
303 // x0 += x4, x12 = rotl32(x12 ^ x0, 8)
329 // x8 += x12, x4 = rotl32(x4 ^ x8, 7)
357 // x1 += x6, x12 = rotl32(x12 ^ x1, 16)
376 // x11 += x12, x6 = rotl32(x6 ^ x11, 12)
401 // x1 += x6, x12 = rotl32(x12 ^ x1, 8)
427 // x11 += x12, x6 = rotl32(x6 ^ x11, 7)
458 // Also add the counter values 0-3 to x12[0-3].
462 vzip.32 q4, q5 // => (4 5 4 5) (4 5 4 5)
464 vadd.u32 q12, q8 // x12 += counter values 0-3
517 // x12..15[0-3] += s12..15[0-3] (add orig state to 4th row of each block)
583 // Process the final block if processing less than 4 full blocks.
638 .byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17
642 .byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17