Lines Matching +full:0 +full:x0001000
13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
105 interrupts = <0 7 4>;
115 reg = <0xe0008000 0x1000>;
116 interrupts = <0 28 4>;
118 tx-fifo-depth = <0x40>;
119 rx-fifo-depth = <0x40>;
127 reg = <0xe0009000 0x1000>;
128 interrupts = <0 51 4>;
130 tx-fifo-depth = <0x40>;
131 rx-fifo-depth = <0x40>;
142 interrupts = <0 20 4>;
143 reg = <0xe000a000 0x1000>;
151 interrupts = <0 25 4>;
152 reg = <0xe0004000 0x1000>;
154 #size-cells = <0>;
162 interrupts = <0 48 4>;
163 reg = <0xe0005000 0x1000>;
165 #size-cells = <0>;
172 reg = <0xF8F01000 0x1000>,
173 <0xF8F00100 0x100>;
178 reg = <0xF8F02000 0x1000>;
179 interrupts = <0 2 4>;
188 reg = <0xf8006000 0x1000>;
196 reg = <0xE0000000 0x1000>;
197 interrupts = <0 27 4>;
205 reg = <0xE0001000 0x1000>;
206 interrupts = <0 50 4>;
211 reg = <0xe0006000 0x1000>;
214 interrupts = <0 26 4>;
218 #size-cells = <0>;
223 reg = <0xe0007000 0x1000>;
226 interrupts = <0 49 4>;
230 #size-cells = <0>;
235 reg = <0xe000b000 0x1000>;
237 interrupts = <0 22 4>;
241 #size-cells = <0>;
246 reg = <0xe000c000 0x1000>;
248 interrupts = <0 45 4>;
252 #size-cells = <0>;
257 reg = <0xe000e000 0x0001000>;
261 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
262 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
263 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
267 nfc0: nand-controller@0,0 {
269 reg = <0 0 0x1000000>;
272 #size-cells = <0>;
282 interrupts = <0 24 4>;
283 reg = <0xe0100000 0x1000>;
292 interrupts = <0 47 4>;
293 reg = <0xe0101000 0x1000>;
300 reg = <0xF8000000 0x1000>;
305 fclk-enable = <0>;
317 reg = <0x100 0x100>;
322 reg = <0x200 0x48>;
329 reg = <0x700 0x200>;
336 reg = <0xf8003000 0x1000>;
340 interrupts = <0 13 4>,
341 <0 14 4>, <0 15 4>,
342 <0 16 4>, <0 17 4>,
343 <0 40 4>, <0 41 4>,
344 <0 42 4>, <0 43 4>;
352 reg = <0xf8007000 0x100>;
354 interrupts = <0 8 4>;
362 reg = <0xf8f00200 0x20>;
363 interrupts = <1 11 0x301>;
370 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
373 reg = <0xF8001000 0x1000>;
378 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
381 reg = <0xF8002000 0x1000>;
386 interrupts = <1 13 0x301>;
388 reg = <0xf8f00600 0x20>;
397 interrupts = <0 21 4>;
398 reg = <0xe0002000 0x1000>;
407 interrupts = <0 44 4>;
408 reg = <0xe0003000 0x1000>;
416 interrupts = <0 9 1>;
417 reg = <0xf8005000 0x1000>;
423 reg = <0xf8801000 0x1000>;
437 reg = <0xf8803000 0x1000>;
451 reg = <0xf8804000 0x1000>;
467 #size-cells = <0>;
470 port@0 {
471 reg = <0>;
495 reg = <0xf889c000 0x1000>;
510 reg = <0xf889d000 0x1000>;