Lines Matching +full:0 +full:x10002000
24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
73 ranges = <0x0 0x10000000 0x200>;
77 led@8,0 {
79 reg = <0x08 0x04>;
80 offset = <0x08>;
81 mask = <0x01>;
82 label = "versatile:0";
88 reg = <0x08 0x04>;
89 offset = <0x08>;
90 mask = <0x02>;
97 reg = <0x08 0x04>;
98 offset = <0x08>;
99 mask = <0x04>;
106 reg = <0x08 0x04>;
107 offset = <0x08>;
108 mask = <0x08>;
114 reg = <0x08 0x04>;
115 offset = <0x08>;
116 mask = <0x10>;
122 reg = <0x08 0x04>;
123 offset = <0x08>;
124 mask = <0x20>;
130 reg = <0x08 0x04>;
131 offset = <0x08>;
132 mask = <0x40>;
138 reg = <0x08 0x04>;
139 offset = <0x08>;
140 mask = <0x80>;
147 #clock-cells = <0>;
154 #clock-cells = <0>;
162 #clock-cells = <0>;
173 reg = <0x34000000 0x04000000>;
182 #size-cells = <0>;
184 reg = <0x10002000 0x1000>;
188 reg = <0x68>;
194 reg = <0x10010000 0x10000>;
200 reg = <0x10008000 0x1000>;
213 reg = <0x10140000 0x1000>;
214 valid-mask = <0xffffffff>;
221 reg = <0x10003000 0x1000>;
224 clear-mask = <0xffffffff>;
229 valid-mask = <0x0760031b>;
234 reg = <0x10130000 0x1000>;
242 reg = <0x101f1000 0x1000>;
250 reg = <0x101f2000 0x1000>;
258 reg = <0x101f3000 0x1000>;
266 reg = <0x10100000 0x1000>;
273 reg = <0x10110000 0x1000>;
280 reg = <0x10120000 0x1000>;
301 port@0 {
303 #size-cells = <0>;
305 clcd_pads_panel: endpoint@0 {
306 reg = <0>;
308 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
313 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
320 reg = <0x101e0000 0x1000>;
327 reg = <0x101e1000 0x1000>;
328 interrupts = <0>;
335 reg = <0x101e2000 0x1000>;
343 reg = <0x101e3000 0x1000>;
351 reg = <0x101e4000 0x1000>;
363 reg = <0x101e5000 0x1000>;
375 reg = <0x101e8000 0x1000>;
383 reg = <0x101f0000 0x1000>;
391 reg = <0x101f4000 0x1000>;
401 ranges = <0 0x10000000 0x10000>;
403 sysreg@0 {
405 reg = <0x00000 0x1000>;
407 panel: display@0 {
420 reg = <0x4000 0x1000>;
427 reg = <0x5000 0x1000>;
434 reg = <0x6000 0x1000>;
442 reg = <0x7000 0x1000>;