Lines Matching +full:reset +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a9";
26 enable-method = "psci";
27 next-level-cache = <&l2>;
28 operating-points-v2 = <&cpu_opp>;
29 #cooling-cells = <2>;
34 compatible = "arm,cortex-a9";
37 enable-method = "psci";
38 next-level-cache = <&l2>;
39 operating-points-v2 = <&cpu_opp>;
40 #cooling-cells = <2>;
45 compatible = "arm,cortex-a9";
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cpu_opp>;
51 #cooling-cells = <2>;
56 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu_opp>;
62 #cooling-cells = <2>;
66 cpu_opp: opp-table {
67 compatible = "operating-points-v2";
68 opp-shared;
70 opp-100000000 {
71 opp-hz = /bits/ 64 <100000000>;
72 clock-latency-ns = <300>;
74 opp-150000000 {
75 opp-hz = /bits/ 64 <150000000>;
76 clock-latency-ns = <300>;
78 opp-200000000 {
79 opp-hz = /bits/ 64 <200000000>;
80 clock-latency-ns = <300>;
82 opp-300000000 {
83 opp-hz = /bits/ 64 <300000000>;
84 clock-latency-ns = <300>;
86 opp-400000000 {
87 opp-hz = /bits/ 64 <400000000>;
88 clock-latency-ns = <300>;
90 opp-600000000 {
91 opp-hz = /bits/ 64 <600000000>;
92 clock-latency-ns = <300>;
94 opp-800000000 {
95 opp-hz = /bits/ 64 <800000000>;
96 clock-latency-ns = <300>;
98 opp-1200000000 {
99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
105 compatible = "arm,psci-0.2";
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <25000000>;
116 arm_timer_clk: arm-timer {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <50000000>;
123 thermal-zones {
124 cpu-thermal {
125 polling-delay-passive = <250>; /* 250ms */
126 polling-delay = <1000>; /* 1000ms */
127 thermal-sensors = <&pvtctl>;
130 cpu_crit: cpu-crit {
135 cpu_alert: cpu-alert {
142 cooling-maps {
145 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
159 interrupt-parent = <&intc>;
161 l2: cache-controller@500c0000 {
162 compatible = "socionext,uniphier-system-cache";
169 cache-unified;
170 cache-size = <(1280 * 1024)>;
171 cache-sets = <512>;
172 cache-line-size = <128>;
173 cache-level = <2>;
177 compatible = "socionext,uniphier-scssi";
180 #address-cells = <1>;
181 #size-cells = <0>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_spi0>;
190 compatible = "socionext,uniphier-scssi";
193 #address-cells = <1>;
194 #size-cells = <0>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_spi1>;
203 compatible = "socionext,uniphier-uart";
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart0>;
214 compatible = "socionext,uniphier-uart";
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_uart1>;
225 compatible = "socionext,uniphier-uart";
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_uart2>;
236 compatible = "socionext,uniphier-uart";
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_uart3>;
247 compatible = "socionext,uniphier-gpio";
249 interrupt-parent = <&aidet>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 gpio-ranges = <&pinctrl 0 0 0>,
256 gpio-ranges-group-names = "gpio_range0",
259 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
264 compatible = "socionext,uniphier-pxs2-aio";
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_ain1>,
275 clock-names = "aio";
277 reset-names = "aio";
279 #sound-dai-cells = <1>;
319 compatible = "socionext,uniphier-fi2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c0>;
329 clock-frequency = <100000>;
333 compatible = "socionext,uniphier-fi2c";
336 #address-cells = <1>;
337 #size-cells = <0>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_i2c1>;
343 clock-frequency = <100000>;
347 compatible = "socionext,uniphier-fi2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_i2c2>;
357 clock-frequency = <100000>;
361 compatible = "socionext,uniphier-fi2c";
364 #address-cells = <1>;
365 #size-cells = <0>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_i2c3>;
371 clock-frequency = <100000>;
374 /* chip-internal connection for DMD */
376 compatible = "socionext,uniphier-fi2c";
378 #address-cells = <1>;
379 #size-cells = <0>;
383 clock-frequency = <400000>;
386 /* chip-internal connection for STM */
388 compatible = "socionext,uniphier-fi2c";
390 #address-cells = <1>;
391 #size-cells = <0>;
395 clock-frequency = <400000>;
398 /* chip-internal connection for HDMI */
400 compatible = "socionext,uniphier-fi2c";
402 #address-cells = <1>;
403 #size-cells = <0>;
407 clock-frequency = <400000>;
410 system_bus: system-bus@58c00000 {
411 compatible = "socionext,uniphier-system-bus";
414 #address-cells = <2>;
415 #size-cells = <1>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_system_bus>;
421 compatible = "socionext,uniphier-smpctrl";
426 compatible = "socionext,uniphier-pxs2-sdctrl",
427 "simple-mfd", "syscon";
431 compatible = "socionext,uniphier-pxs2-sd-clock";
432 #clock-cells = <1>;
435 sd_rst: reset {
436 compatible = "socionext,uniphier-pxs2-sd-reset";
437 #reset-cells = <1>;
442 compatible = "socionext,uniphier-pxs2-perictrl",
443 "simple-mfd", "syscon";
447 compatible = "socionext,uniphier-pxs2-peri-clock";
448 #clock-cells = <1>;
451 peri_rst: reset {
452 compatible = "socionext,uniphier-pxs2-peri-reset";
453 #reset-cells = <1>;
458 compatible = "socionext,uniphier-sd-v3.1.1";
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_emmc>;
465 reset-names = "host", "hw";
467 bus-width = <8>;
468 cap-mmc-highspeed;
469 cap-mmc-hw-reset;
470 non-removable;
474 compatible = "socionext,uniphier-sd-v3.1.1";
478 pinctrl-names = "default", "uhs";
479 pinctrl-0 = <&pinctrl_sd>;
480 pinctrl-1 = <&pinctrl_sd_uhs>;
482 reset-names = "host";
484 bus-width = <4>;
485 cap-sd-highspeed;
486 sd-uhs-sdr12;
487 sd-uhs-sdr25;
488 sd-uhs-sdr50;
491 soc_glue: soc-glue@5f800000 {
492 compatible = "socionext,uniphier-pxs2-soc-glue",
493 "simple-mfd", "syscon";
497 compatible = "socionext,uniphier-pxs2-pinctrl";
501 soc-glue@5f900000 {
502 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
503 "simple-mfd";
504 #address-cells = <1>;
505 #size-cells = <1>;
509 compatible = "socionext,uniphier-efuse";
514 compatible = "socionext,uniphier-efuse";
519 xdmac: dma-controller@5fc10000 {
520 compatible = "socionext,uniphier-xdmac";
523 dma-channels = <16>;
524 #dma-cells = <2>;
527 aidet: interrupt-controller@5fc20000 {
528 compatible = "socionext,uniphier-pxs2-aidet";
530 interrupt-controller;
531 #interrupt-cells = <2>;
535 compatible = "arm,cortex-a9-global-timer";
543 compatible = "arm,cortex-a9-twd-timer";
550 intc: interrupt-controller@60001000 {
551 compatible = "arm,cortex-a9-gic";
554 #interrupt-cells = <3>;
555 interrupt-controller;
559 compatible = "socionext,uniphier-pxs2-sysctrl",
560 "simple-mfd", "syscon";
564 compatible = "socionext,uniphier-pxs2-clock";
565 #clock-cells = <1>;
568 sys_rst: reset {
569 compatible = "socionext,uniphier-pxs2-reset";
570 #reset-cells = <1>;
573 pvtctl: thermal-sensor {
574 compatible = "socionext,uniphier-pxs2-thermal";
576 #thermal-sensor-cells = <0>;
577 socionext,tmod-calibration = <0x0f86 0x6844>;
582 compatible = "socionext,uniphier-pxs2-ave4";
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_ether_rgmii>;
588 clock-names = "ether";
590 reset-names = "ether";
592 phy-mode = "rgmii-id";
593 local-mac-address = [00 00 00 00 00 00];
594 socionext,syscon-phy-mode = <&soc_glue 0>;
597 #address-cells = <1>;
598 #size-cells = <0>;
603 compatible = "socionext,uniphier-pxs2-ahci",
604 "generic-ahci";
610 ports-implemented = <1>;
614 sata-controller@65700000 {
615 compatible = "socionext,uniphier-pxs2-ahci-glue",
616 "simple-mfd";
617 #address-cells = <1>;
618 #size-cells = <1>;
621 ahci_rst: reset-controller@0 {
622 compatible = "socionext,uniphier-pxs2-ahci-reset";
624 clock-names = "link";
626 reset-names = "link";
628 #reset-cells = <1>;
631 ahci_phy: sata-phy@10 {
632 compatible = "socionext,uniphier-pxs2-ahci-phy";
634 clock-names = "link";
636 reset-names = "link", "phy";
638 #phy-cells = <0>;
643 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
646 interrupt-names = "dwc_usb3";
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
650 clock-names = "ref", "bus_early", "suspend";
658 usb-controller@65b00000 {
659 compatible = "socionext,uniphier-pxs2-dwc3-glue",
660 "simple-mfd";
661 #address-cells = <1>;
662 #size-cells = <1>;
665 usb0_rst: reset@0 {
666 compatible = "socionext,uniphier-pxs2-usb3-reset";
668 #reset-cells = <1>;
669 clock-names = "link";
671 reset-names = "link";
676 compatible = "socionext,uniphier-pxs2-usb3-regulator";
678 clock-names = "link";
680 reset-names = "link";
685 compatible = "socionext,uniphier-pxs2-usb3-regulator";
687 clock-names = "link";
689 reset-names = "link";
693 usb0_hsphy0: hs-phy@200 {
694 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
696 #phy-cells = <0>;
697 clock-names = "link", "phy";
699 reset-names = "link", "phy";
701 vbus-supply = <&usb0_vbus0>;
704 usb0_hsphy1: hs-phy@210 {
705 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
707 #phy-cells = <0>;
708 clock-names = "link", "phy";
710 reset-names = "link", "phy";
712 vbus-supply = <&usb0_vbus1>;
715 usb0_ssphy0: ss-phy@300 {
716 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
718 #phy-cells = <0>;
719 clock-names = "link", "phy";
721 reset-names = "link", "phy";
723 vbus-supply = <&usb0_vbus0>;
726 usb0_ssphy1: ss-phy@310 {
727 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
729 #phy-cells = <0>;
730 clock-names = "link", "phy";
732 reset-names = "link", "phy";
734 vbus-supply = <&usb0_vbus1>;
739 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
742 interrupt-names = "dwc_usb3";
744 pinctrl-names = "default";
745 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
746 clock-names = "ref", "bus_early", "suspend";
753 usb-controller@65d00000 {
754 compatible = "socionext,uniphier-pxs2-dwc3-glue",
755 "simple-mfd";
756 #address-cells = <1>;
757 #size-cells = <1>;
760 usb1_rst: reset@0 {
761 compatible = "socionext,uniphier-pxs2-usb3-reset";
763 #reset-cells = <1>;
764 clock-names = "link";
766 reset-names = "link";
771 compatible = "socionext,uniphier-pxs2-usb3-regulator";
773 clock-names = "link";
775 reset-names = "link";
780 compatible = "socionext,uniphier-pxs2-usb3-regulator";
782 clock-names = "link";
784 reset-names = "link";
788 usb1_hsphy0: hs-phy@200 {
789 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
791 #phy-cells = <0>;
792 clock-names = "link", "phy";
794 reset-names = "link", "phy";
796 vbus-supply = <&usb1_vbus0>;
799 usb1_hsphy1: hs-phy@210 {
800 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
802 #phy-cells = <0>;
803 clock-names = "link", "phy";
805 reset-names = "link", "phy";
807 vbus-supply = <&usb1_vbus1>;
810 usb1_ssphy0: ss-phy@300 {
811 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
813 #phy-cells = <0>;
814 clock-names = "link", "phy";
816 reset-names = "link", "phy";
818 vbus-supply = <&usb1_vbus0>;
822 nand: nand-controller@68000000 {
823 compatible = "socionext,uniphier-denali-nand-v5b";
825 reg-names = "nand_data", "denali_reg";
827 #address-cells = <1>;
828 #size-cells = <0>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&pinctrl_nand>;
832 clock-names = "nand", "nand_x", "ecc";
834 reset-names = "nand", "reg";
840 #include "uniphier-pinctrl.dtsi"