Lines Matching +full:opp +full:- +full:600000000
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
40 cpu_opp: opp-table {
41 compatible = "operating-points-v2";
42 opp-shared;
44 opp-100000000 {
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
48 opp-116667000 {
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
52 opp-150000000 {
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
56 opp-175000000 {
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
60 opp-200000000 {
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
64 opp-233334000 {
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
68 opp-300000000 {
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
72 opp-350000000 {
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
76 opp-400000000 {
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
80 opp-466667000 {
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
84 opp-600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
88 opp-700000000 {
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
92 opp-800000000 {
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
96 opp-933334000 {
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
100 opp-1200000000 {
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
104 opp-1400000000 {
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
111 compatible = "arm,psci-0.2";
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <20000000>;
122 arm_timer_clk: arm-timer {
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
134 interrupt-parent = <&intc>;
136 l2: cache-controller@500c0000 {
137 compatible = "socionext,uniphier-system-cache";
142 cache-unified;
143 cache-size = <(2 * 1024 * 1024)>;
144 cache-sets = <512>;
145 cache-line-size = <128>;
146 cache-level = <2>;
147 next-level-cache = <&l3>;
150 l3: cache-controller@500c8000 {
151 compatible = "socionext,uniphier-system-cache";
156 cache-unified;
157 cache-size = <(2 * 1024 * 1024)>;
158 cache-sets = <512>;
159 cache-line-size = <256>;
160 cache-level = <3>;
164 compatible = "socionext,uniphier-scssi";
167 #address-cells = <1>;
168 #size-cells = <0>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_spi0>;
177 compatible = "socionext,uniphier-scssi";
180 #address-cells = <1>;
181 #size-cells = <0>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_spi1>;
190 compatible = "socionext,uniphier-uart";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart0>;
201 compatible = "socionext,uniphier-uart";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart1>;
212 compatible = "socionext,uniphier-uart";
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart2>;
223 compatible = "socionext,uniphier-uart";
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_uart3>;
234 compatible = "socionext,uniphier-gpio";
236 interrupt-parent = <&aidet>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-controller;
240 #gpio-cells = <2>;
241 gpio-ranges = <&pinctrl 0 0 0>;
242 gpio-ranges-group-names = "gpio_range";
244 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
248 compatible = "socionext,uniphier-fi2c";
251 #address-cells = <1>;
252 #size-cells = <0>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c0>;
258 clock-frequency = <100000>;
262 compatible = "socionext,uniphier-fi2c";
265 #address-cells = <1>;
266 #size-cells = <0>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c1>;
272 clock-frequency = <100000>;
276 compatible = "socionext,uniphier-fi2c";
279 #address-cells = <1>;
280 #size-cells = <0>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_i2c2>;
286 clock-frequency = <100000>;
290 compatible = "socionext,uniphier-fi2c";
293 #address-cells = <1>;
294 #size-cells = <0>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c3>;
300 clock-frequency = <100000>;
305 /* chip-internal connection for DMD */
307 compatible = "socionext,uniphier-fi2c";
309 #address-cells = <1>;
310 #size-cells = <0>;
314 clock-frequency = <400000>;
317 /* chip-internal connection for HDMI */
319 compatible = "socionext,uniphier-fi2c";
321 #address-cells = <1>;
322 #size-cells = <0>;
326 clock-frequency = <400000>;
329 system_bus: system-bus@58c00000 {
330 compatible = "socionext,uniphier-system-bus";
333 #address-cells = <2>;
334 #size-cells = <1>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_system_bus>;
340 compatible = "socionext,uniphier-smpctrl";
345 compatible = "socionext,uniphier-pro5-sdctrl",
346 "simple-mfd", "syscon";
350 compatible = "socionext,uniphier-pro5-sd-clock";
351 #clock-cells = <1>;
355 compatible = "socionext,uniphier-pro5-sd-reset";
356 #reset-cells = <1>;
361 compatible = "socionext,uniphier-pro5-perictrl",
362 "simple-mfd", "syscon";
366 compatible = "socionext,uniphier-pro5-peri-clock";
367 #clock-cells = <1>;
371 compatible = "socionext,uniphier-pro5-peri-reset";
372 #reset-cells = <1>;
376 soc-glue@5f800000 {
377 compatible = "socionext,uniphier-pro5-soc-glue",
378 "simple-mfd", "syscon";
382 compatible = "socionext,uniphier-pro5-pinctrl";
386 soc-glue@5f900000 {
387 compatible = "socionext,uniphier-pro5-soc-glue-debug",
388 "simple-mfd";
389 #address-cells = <1>;
390 #size-cells = <1>;
394 compatible = "socionext,uniphier-efuse";
399 compatible = "socionext,uniphier-efuse";
404 compatible = "socionext,uniphier-efuse";
409 compatible = "socionext,uniphier-efuse";
414 compatible = "socionext,uniphier-efuse";
419 xdmac: dma-controller@5fc10000 {
420 compatible = "socionext,uniphier-xdmac";
423 dma-channels = <16>;
424 #dma-cells = <2>;
427 aidet: interrupt-controller@5fc20000 {
428 compatible = "socionext,uniphier-pro5-aidet";
430 interrupt-controller;
431 #interrupt-cells = <2>;
435 compatible = "arm,cortex-a9-global-timer";
443 compatible = "arm,cortex-a9-twd-timer";
450 intc: interrupt-controller@60001000 {
451 compatible = "arm,cortex-a9-gic";
454 #interrupt-cells = <3>;
455 interrupt-controller;
459 compatible = "socionext,uniphier-pro5-sysctrl",
460 "simple-mfd", "syscon";
464 compatible = "socionext,uniphier-pro5-clock";
465 #clock-cells = <1>;
469 compatible = "socionext,uniphier-pro5-reset";
470 #reset-cells = <1>;
475 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
478 interrupt-names = "host";
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_usb0>;
482 clock-names = "ref", "bus_early", "suspend";
489 usb-controller@65b00000 {
490 compatible = "socionext,uniphier-pro5-dwc3-glue",
491 "simple-mfd";
492 #address-cells = <1>;
493 #size-cells = <1>;
497 compatible = "socionext,uniphier-pro5-usb3-reset";
499 #reset-cells = <1>;
500 clock-names = "gio", "link";
502 reset-names = "gio", "link";
507 compatible = "socionext,uniphier-pro5-usb3-regulator";
509 clock-names = "gio", "link";
511 reset-names = "gio", "link";
515 usb0_hsphy0: hs-phy@280 {
516 compatible = "socionext,uniphier-pro5-usb3-hsphy";
518 #phy-cells = <0>;
519 clock-names = "gio", "link";
521 reset-names = "gio", "link";
523 vbus-supply = <&usb0_vbus0>;
526 usb0_ssphy0: ss-phy@380 {
527 compatible = "socionext,uniphier-pro5-usb3-ssphy";
529 #phy-cells = <0>;
530 clock-names = "gio", "link";
532 reset-names = "gio", "link";
534 vbus-supply = <&usb0_vbus0>;
539 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
542 interrupt-names = "host";
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
546 clock-names = "ref", "bus_early", "suspend";
553 usb-controller@65d00000 {
554 compatible = "socionext,uniphier-pro5-dwc3-glue",
555 "simple-mfd";
556 #address-cells = <1>;
557 #size-cells = <1>;
561 compatible = "socionext,uniphier-pro5-usb3-reset";
563 #reset-cells = <1>;
564 clock-names = "gio", "link";
566 reset-names = "gio", "link";
571 compatible = "socionext,uniphier-pro5-usb3-regulator";
573 clock-names = "gio", "link";
575 reset-names = "gio", "link";
580 compatible = "socionext,uniphier-pro5-usb3-regulator";
582 clock-names = "gio", "link";
584 reset-names = "gio", "link";
588 usb1_hsphy0: hs-phy@280 {
589 compatible = "socionext,uniphier-pro5-usb3-hsphy";
591 #phy-cells = <0>;
592 clock-names = "gio", "link";
594 reset-names = "gio", "link";
596 vbus-supply = <&usb1_vbus0>;
599 usb1_hsphy1: hs-phy@290 {
600 compatible = "socionext,uniphier-pro5-usb3-hsphy";
602 #phy-cells = <0>;
603 clock-names = "gio", "link";
605 reset-names = "gio", "link";
607 vbus-supply = <&usb1_vbus1>;
610 usb1_ssphy0: ss-phy@380 {
611 compatible = "socionext,uniphier-pro5-usb3-ssphy";
613 #phy-cells = <0>;
614 clock-names = "gio", "link";
616 reset-names = "gio", "link";
618 vbus-supply = <&usb1_vbus0>;
622 pcie_ep: pcie-ep@66000000 {
623 compatible = "socionext,uniphier-pro5-pcie-ep";
625 reg-names = "dbi", "dbi2", "link", "addr_space";
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_pcie>;
630 clock-names = "gio", "link";
632 reset-names = "gio", "link";
634 num-ib-windows = <16>;
635 num-ob-windows = <16>;
636 num-lanes = <4>;
637 phy-names = "pcie-phy";
642 compatible = "socionext,uniphier-pro5-pcie-phy";
644 #phy-cells = <0>;
645 clock-names = "gio", "link";
647 reset-names = "gio", "link";
651 nand: nand-controller@68000000 {
652 compatible = "socionext,uniphier-denali-nand-v5b";
654 reg-names = "nand_data", "denali_reg";
656 #address-cells = <1>;
657 #size-cells = <0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&pinctrl_nand>;
661 clock-names = "nand", "nand_x", "ecc";
663 reset-names = "nand", "reg";
668 compatible = "socionext,uniphier-sd-v3.1";
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_emmc>;
675 reset-names = "host", "hw";
677 bus-width = <8>;
678 cap-mmc-highspeed;
679 cap-mmc-hw-reset;
680 non-removable;
684 compatible = "socionext,uniphier-sd-v3.1";
688 pinctrl-names = "default", "uhs";
689 pinctrl-0 = <&pinctrl_sd>;
690 pinctrl-1 = <&pinctrl_sd_uhs>;
692 reset-names = "host";
694 bus-width = <4>;
695 cap-sd-highspeed;
696 sd-uhs-sdr12;
697 sd-uhs-sdr25;
698 sd-uhs-sdr50;
703 #include "uniphier-pinctrl.dtsi"