Lines Matching +full:simple +full:- +full:mfd
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
30 compatible = "arm,cortex-a9";
32 enable-method = "psci";
33 next-level-cache = <&l2>;
38 compatible = "arm,psci-0.2";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
49 arm_timer_clk: arm-timer {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
61 interrupt-parent = <&intc>;
63 l2: cache-controller@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
69 cache-unified;
70 cache-size = <(768 * 1024)>;
71 cache-sets = <256>;
72 cache-line-size = <128>;
73 cache-level = <2>;
77 compatible = "socionext,uniphier-scssi";
80 #address-cells = <1>;
81 #size-cells = <0>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_spi0>;
90 compatible = "socionext,uniphier-uart";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart0>;
101 compatible = "socionext,uniphier-uart";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart1>;
112 compatible = "socionext,uniphier-uart";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
123 compatible = "socionext,uniphier-uart";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_uart3>;
134 compatible = "socionext,uniphier-gpio";
136 interrupt-parent = <&aidet>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 gpio-ranges = <&pinctrl 0 0 0>;
142 gpio-ranges-group-names = "gpio_range";
144 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
148 compatible = "socionext,uniphier-fi2c";
151 #address-cells = <1>;
152 #size-cells = <0>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c0>;
158 clock-frequency = <100000>;
162 compatible = "socionext,uniphier-fi2c";
165 #address-cells = <1>;
166 #size-cells = <0>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
172 clock-frequency = <100000>;
176 compatible = "socionext,uniphier-fi2c";
179 #address-cells = <1>;
180 #size-cells = <0>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_i2c2>;
186 clock-frequency = <100000>;
190 compatible = "socionext,uniphier-fi2c";
193 #address-cells = <1>;
194 #size-cells = <0>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
200 clock-frequency = <100000>;
205 /* chip-internal connection for DMD */
207 compatible = "socionext,uniphier-fi2c";
209 #address-cells = <1>;
210 #size-cells = <0>;
214 clock-frequency = <400000>;
217 /* chip-internal connection for HDMI */
219 compatible = "socionext,uniphier-fi2c";
221 #address-cells = <1>;
222 #size-cells = <0>;
226 clock-frequency = <400000>;
229 system_bus: system-bus@58c00000 {
230 compatible = "socionext,uniphier-system-bus";
233 #address-cells = <2>;
234 #size-cells = <1>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_system_bus>;
240 compatible = "socionext,uniphier-smpctrl";
245 compatible = "socionext,uniphier-pro4-mioctrl",
246 "simple-mfd", "syscon";
250 compatible = "socionext,uniphier-pro4-mio-clock";
251 #clock-cells = <1>;
255 compatible = "socionext,uniphier-pro4-mio-reset";
256 #reset-cells = <1>;
261 compatible = "socionext,uniphier-pro4-perictrl",
262 "simple-mfd", "syscon";
266 compatible = "socionext,uniphier-pro4-peri-clock";
267 #clock-cells = <1>;
271 compatible = "socionext,uniphier-pro4-peri-reset";
272 #reset-cells = <1>;
276 dmac: dma-controller@5a000000 {
277 compatible = "socionext,uniphier-mio-dmac";
289 #dma-cells = <1>;
293 compatible = "socionext,uniphier-sd-v2.91";
297 pinctrl-names = "default", "uhs";
298 pinctrl-0 = <&pinctrl_sd>;
299 pinctrl-1 = <&pinctrl_sd_uhs>;
301 reset-names = "host", "bridge";
303 dma-names = "rx-tx";
305 bus-width = <4>;
306 cap-sd-highspeed;
307 sd-uhs-sdr12;
308 sd-uhs-sdr25;
309 sd-uhs-sdr50;
313 compatible = "socionext,uniphier-sd-v2.91";
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_emmc>;
320 reset-names = "host", "bridge", "hw";
322 dma-names = "rx-tx";
324 bus-width = <8>;
325 cap-mmc-highspeed;
326 cap-mmc-hw-reset;
327 non-removable;
331 compatible = "socionext,uniphier-sd-v2.91";
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_sd1>;
338 reset-names = "host", "bridge";
340 dma-names = "rx-tx";
342 bus-width = <4>;
343 cap-sd-highspeed;
347 compatible = "socionext,uniphier-ehci", "generic-ehci";
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usb2>;
357 phy-names = "usb";
359 has-transaction-translator;
363 compatible = "socionext,uniphier-ehci", "generic-ehci";
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_usb3>;
373 phy-names = "usb";
375 has-transaction-translator;
378 soc_glue: soc-glue@5f800000 {
379 compatible = "socionext,uniphier-pro4-soc-glue",
380 "simple-mfd", "syscon";
384 compatible = "socionext,uniphier-pro4-pinctrl";
387 usb-controller {
388 compatible = "socionext,uniphier-pro4-usb2-phy";
389 #address-cells = <1>;
390 #size-cells = <0>;
394 #phy-cells = <0>;
399 #phy-cells = <0>;
404 #phy-cells = <0>;
405 vbus-supply = <&usb0_vbus>;
410 #phy-cells = <0>;
411 vbus-supply = <&usb1_vbus>;
416 compatible = "socionext,uniphier-pro4-sg-clock";
417 #clock-cells = <1>;
421 soc-glue@5f900000 {
422 compatible = "socionext,uniphier-pro4-soc-glue-debug",
423 "simple-mfd";
424 #address-cells = <1>;
425 #size-cells = <1>;
429 compatible = "socionext,uniphier-efuse";
434 compatible = "socionext,uniphier-efuse";
439 compatible = "socionext,uniphier-efuse";
444 xdmac: dma-controller@5fc10000 {
445 compatible = "socionext,uniphier-xdmac";
448 dma-channels = <16>;
449 #dma-cells = <2>;
452 aidet: interrupt-controller@5fc20000 {
453 compatible = "socionext,uniphier-pro4-aidet";
455 interrupt-controller;
456 #interrupt-cells = <2>;
460 compatible = "arm,cortex-a9-global-timer";
468 compatible = "arm,cortex-a9-twd-timer";
475 intc: interrupt-controller@60001000 {
476 compatible = "arm,cortex-a9-gic";
479 #interrupt-cells = <3>;
480 interrupt-controller;
484 compatible = "socionext,uniphier-pro4-sysctrl",
485 "simple-mfd", "syscon";
489 compatible = "socionext,uniphier-pro4-clock";
490 #clock-cells = <1>;
494 compatible = "socionext,uniphier-pro4-reset";
495 #reset-cells = <1>;
500 compatible = "socionext,uniphier-pro4-ave4";
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_ether_rgmii>;
506 clock-names = "gio", "ether", "ether-gb", "ether-phy";
509 reset-names = "gio", "ether";
511 phy-mode = "rgmii";
512 local-mac-address = [00 00 00 00 00 00];
513 socionext,syscon-phy-mode = <&soc_glue 0>;
516 #address-cells = <1>;
517 #size-cells = <0>;
522 compatible = "socionext,uniphier-pro4-ahci",
523 "generic-ahci";
529 ports-implemented = <1>;
531 assigned-clocks = <&sg_clk 0>;
532 assigned-clock-rates = <25000000>;
535 sata-controller@65700000 {
536 compatible = "socionext,uniphier-pxs2-ahci-glue",
537 "simple-mfd";
538 #address-cells = <1>;
539 #size-cells = <1>;
542 ahci0_rst: reset-controller@0 {
543 compatible = "socionext,uniphier-pro4-ahci-reset";
545 clock-names = "gio", "link";
547 reset-names = "gio", "link";
549 #reset-cells = <1>;
552 ahci0_phy: sata-phy@10 {
553 compatible = "socionext,uniphier-pro4-ahci-phy";
555 clock-names = "link", "gio";
557 reset-names = "link", "gio", "phy",
563 #phy-cells = <0>;
568 compatible = "socionext,uniphier-pro4-ahci",
569 "generic-ahci";
575 ports-implemented = <1>;
577 assigned-clocks = <&sg_clk 0>;
578 assigned-clock-rates = <25000000>;
581 sata-controller@65900000 {
582 compatible = "socionext,uniphier-pro4-ahci-glue",
583 "simple-mfd";
584 #address-cells = <1>;
585 #size-cells = <1>;
588 ahci1_rst: reset-controller@0 {
589 compatible = "socionext,uniphier-pro4-ahci-reset";
591 clock-names = "gio", "link";
593 reset-names = "gio", "link";
595 #reset-cells = <1>;
598 ahci1_phy: sata-phy@10 {
599 compatible = "socionext,uniphier-pro4-ahci-phy";
601 clock-names = "link", "gio";
603 reset-names = "link", "gio", "phy",
609 #phy-cells = <0>;
614 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
617 interrupt-names = "host", "peripheral";
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_usb0>;
622 clock-names = "ref", "bus_early", "suspend";
629 usb-controller@65b00000 {
630 compatible = "socionext,uniphier-pro4-dwc3-glue",
631 "simple-mfd";
632 #address-cells = <1>;
633 #size-cells = <1>;
637 compatible = "socionext,uniphier-pro4-usb3-regulator";
639 clock-names = "gio", "link";
641 reset-names = "gio", "link";
645 usb0_ssphy: ss-phy@10 {
646 compatible = "socionext,uniphier-pro4-usb3-ssphy";
648 #phy-cells = <0>;
649 clock-names = "gio", "link";
651 reset-names = "gio", "link";
653 vbus-supply = <&usb0_vbus>;
657 compatible = "socionext,uniphier-pro4-usb3-reset";
659 #reset-cells = <1>;
660 clock-names = "gio", "link";
662 reset-names = "gio", "link";
668 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
671 interrupt-names = "host", "peripheral";
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_usb1>;
676 clock-names = "ref", "bus_early", "suspend";
683 usb-controller@65d00000 {
684 compatible = "socionext,uniphier-pro4-dwc3-glue",
685 "simple-mfd";
686 #address-cells = <1>;
687 #size-cells = <1>;
691 compatible = "socionext,uniphier-pro4-usb3-regulator";
693 clock-names = "gio", "link";
695 reset-names = "gio", "link";
700 compatible = "socionext,uniphier-pro4-usb3-reset";
702 #reset-cells = <1>;
703 clock-names = "gio", "link";
705 reset-names = "gio", "link";
710 nand: nand-controller@68000000 {
711 compatible = "socionext,uniphier-denali-nand-v5a";
713 reg-names = "nand_data", "denali_reg";
715 #address-cells = <1>;
716 #size-cells = <0>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_nand>;
720 clock-names = "nand", "nand_x", "ecc";
722 reset-names = "nand", "reg";
728 #include "uniphier-pinctrl.dtsi"