Lines Matching +full:tegra20 +full:- +full:tvo
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
24 compatible = "nvidia,tegra30-pcie";
29 reg-names = "pads", "afi", "cs";
32 interrupt-names = "intr", "msi";
34 #interrupt-cells = <1>;
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
39 #address-cells = <3>;
40 #size-cells = <2>;
46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
53 clock-names = "pex", "afi", "pll_e", "cml";
57 reset-names = "pex", "afi", "pcie_x";
58 power-domains = <&pd_core>;
59 operating-points-v2 = <&pcie_dvfs_opp_table>;
64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
66 bus-range = <0x00 0xff>;
69 #address-cells = <3>;
70 #size-cells = <2>;
73 nvidia,num-lanes = <2>;
78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
80 bus-range = <0x00 0xff>;
83 #address-cells = <3>;
84 #size-cells = <2>;
87 nvidia,num-lanes = <2>;
92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
94 bus-range = <0x00 0xff>;
97 #address-cells = <3>;
98 #size-cells = <2>;
101 nvidia,num-lanes = <2>;
106 compatible = "mmio-sram";
108 #address-cells = <1>;
109 #size-cells = <1>;
119 compatible = "nvidia,tegra30-host1x";
123 interrupt-names = "syncpt", "host1x";
125 clock-names = "host1x";
127 reset-names = "host1x", "mc";
129 power-domains = <&pd_heg>;
130 operating-points-v2 = <&host1x_dvfs_opp_table>;
132 #address-cells = <1>;
133 #size-cells = <1>;
138 compatible = "nvidia,tegra30-mpe";
143 reset-names = "mpe";
144 power-domains = <&pd_mpe>;
145 operating-points-v2 = <&mpe_dvfs_opp_table>;
153 compatible = "nvidia,tegra30-vi";
158 reset-names = "vi";
159 power-domains = <&pd_venc>;
160 operating-points-v2 = <&vi_dvfs_opp_table>;
168 compatible = "nvidia,tegra30-epp";
173 reset-names = "epp";
174 power-domains = <&pd_heg>;
175 operating-points-v2 = <&epp_dvfs_opp_table>;
183 compatible = "nvidia,tegra30-isp";
188 reset-names = "isp";
189 power-domains = <&pd_venc>;
197 compatible = "nvidia,tegra30-gr2d";
202 reset-names = "2d", "mc";
203 power-domains = <&pd_heg>;
204 operating-points-v2 = <&gr2d_dvfs_opp_table>;
210 compatible = "nvidia,tegra30-gr3d";
214 clock-names = "3d", "3d2";
219 reset-names = "3d", "3d2", "mc", "mc2";
220 power-domains = <&pd_3d0>, <&pd_3d1>;
221 power-domain-names = "3d0", "3d1";
222 operating-points-v2 = <&gr3d_dvfs_opp_table>;
229 compatible = "nvidia,tegra30-dc";
234 clock-names = "dc", "parent";
236 reset-names = "dc";
237 power-domains = <&pd_core>;
238 operating-points-v2 = <&disp1_dvfs_opp_table>;
249 interconnect-names = "wina",
251 "winb-vfilter",
261 compatible = "nvidia,tegra30-dc";
266 clock-names = "dc", "parent";
268 reset-names = "dc";
269 power-domains = <&pd_core>;
270 operating-points-v2 = <&disp2_dvfs_opp_table>;
281 interconnect-names = "wina",
283 "winb-vfilter",
293 compatible = "nvidia,tegra30-hdmi";
298 clock-names = "hdmi", "parent";
300 reset-names = "hdmi";
301 power-domains = <&pd_core>;
302 operating-points-v2 = <&hdmi_dvfs_opp_table>;
306 tvo@542c0000 {
307 compatible = "nvidia,tegra30-tvo";
311 power-domains = <&pd_core>;
312 operating-points-v2 = <&tvo_dvfs_opp_table>;
317 compatible = "nvidia,tegra30-dsi";
321 clock-names = "dsi", "parent";
323 reset-names = "dsi";
324 power-domains = <&pd_core>;
325 operating-points-v2 = <&dsia_dvfs_opp_table>;
330 compatible = "nvidia,tegra30-dsi";
334 clock-names = "dsi", "parent";
336 reset-names = "dsi";
337 power-domains = <&pd_core>;
338 operating-points-v2 = <&dsib_dvfs_opp_table>;
344 compatible = "arm,cortex-a9-twd-timer";
346 interrupt-parent = <&intc>;
352 intc: interrupt-controller@50041000 {
353 compatible = "arm,cortex-a9-gic";
356 interrupt-controller;
357 #interrupt-cells = <3>;
358 interrupt-parent = <&intc>;
361 cache-controller@50043000 {
362 compatible = "arm,pl310-cache";
364 arm,data-latency = <6 6 2>;
365 arm,tag-latency = <5 5 2>;
366 cache-unified;
367 cache-level = <2>;
370 lic: interrupt-controller@60004000 {
371 compatible = "nvidia,tegra30-ictlr";
377 interrupt-controller;
378 #interrupt-cells = <3>;
379 interrupt-parent = <&intc>;
383 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
395 compatible = "nvidia,tegra30-car";
397 #clock-cells = <1>;
398 #reset-cells = <1>;
401 compatible = "nvidia,tegra30-sclk";
403 power-domains = <&pd_core>;
404 operating-points-v2 = <&sclk_dvfs_opp_table>;
407 pll-c {
408 compatible = "nvidia,tegra30-pllc";
410 power-domains = <&pd_core>;
411 operating-points-v2 = <&pll_c_dvfs_opp_table>;
414 pll-e {
415 compatible = "nvidia,tegra30-plle";
417 power-domains = <&pd_core>;
418 operating-points-v2 = <&pll_e_dvfs_opp_table>;
421 pll-m {
422 compatible = "nvidia,tegra30-pllm";
424 power-domains = <&pd_core>;
425 operating-points-v2 = <&pll_m_dvfs_opp_table>;
429 flow-controller@60007000 {
430 compatible = "nvidia,tegra30-flowctrl";
435 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
471 reset-names = "dma";
472 #dma-cells = <1>;
476 compatible = "nvidia,tegra30-ahb";
481 compatible = "nvidia,tegra30-actmon";
486 clock-names = "actmon", "emc";
488 reset-names = "actmon";
489 operating-points-v2 = <&emc_bw_dfs_opp_table>;
491 interconnect-names = "cpu-read";
492 #cooling-cells = <2>;
496 compatible = "nvidia,tegra30-gpio";
506 #gpio-cells = <2>;
507 gpio-controller;
508 #interrupt-cells = <2>;
509 interrupt-controller;
510 gpio-ranges = <&pinmux 0 0 248>;
514 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
518 <0x6001c200 0x100>, /* Post-processing Engine */
524 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
528 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
530 interrupt-names = "sync-token", "bsev", "sxe";
532 reset-names = "vde", "mc";
535 power-domains = <&pd_vde>;
536 operating-points-v2 = <&vde_dvfs_opp_table>;
540 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
546 compatible = "nvidia,tegra30-pinmux";
555 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
557 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
560 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
562 reg-shift = <2>;
566 reset-names = "serial";
568 dma-names = "rx", "tx";
573 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
575 reg-shift = <2>;
579 reset-names = "serial";
581 dma-names = "rx", "tx";
586 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
588 reg-shift = <2>;
592 reset-names = "serial";
594 dma-names = "rx", "tx";
599 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
601 reg-shift = <2>;
605 reset-names = "serial";
607 dma-names = "rx", "tx";
612 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
614 reg-shift = <2>;
618 reset-names = "serial";
620 dma-names = "rx", "tx";
625 compatible = "nvidia,tegra30-gmi";
627 #address-cells = <2>;
628 #size-cells = <1>;
631 clock-names = "gmi";
633 reset-names = "gmi";
634 power-domains = <&pd_core>;
635 operating-points-v2 = <&nor_dvfs_opp_table>;
640 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
642 #pwm-cells = <2>;
645 reset-names = "pwm";
646 power-domains = <&pd_core>;
647 operating-points-v2 = <&pwm_dvfs_opp_table>;
652 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
659 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
662 #address-cells = <1>;
663 #size-cells = <0>;
666 clock-names = "div-clk", "fast-clk";
668 reset-names = "i2c";
670 dma-names = "rx", "tx";
675 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
678 #address-cells = <1>;
679 #size-cells = <0>;
682 clock-names = "div-clk", "fast-clk";
684 reset-names = "i2c";
686 dma-names = "rx", "tx";
691 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
694 #address-cells = <1>;
695 #size-cells = <0>;
698 clock-names = "div-clk", "fast-clk";
700 reset-names = "i2c";
702 dma-names = "rx", "tx";
707 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
710 #address-cells = <1>;
711 #size-cells = <0>;
715 reset-names = "i2c";
716 clock-names = "div-clk", "fast-clk";
718 dma-names = "rx", "tx";
723 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
726 #address-cells = <1>;
727 #size-cells = <0>;
730 clock-names = "div-clk", "fast-clk";
732 reset-names = "i2c";
734 dma-names = "rx", "tx";
739 compatible = "nvidia,tegra30-slink";
742 #address-cells = <1>;
743 #size-cells = <0>;
746 reset-names = "spi";
748 dma-names = "rx", "tx";
749 power-domains = <&pd_core>;
750 operating-points-v2 = <&sbc1_dvfs_opp_table>;
755 compatible = "nvidia,tegra30-slink";
758 #address-cells = <1>;
759 #size-cells = <0>;
762 reset-names = "spi";
764 dma-names = "rx", "tx";
765 power-domains = <&pd_core>;
766 operating-points-v2 = <&sbc2_dvfs_opp_table>;
771 compatible = "nvidia,tegra30-slink";
774 #address-cells = <1>;
775 #size-cells = <0>;
778 reset-names = "spi";
780 dma-names = "rx", "tx";
781 power-domains = <&pd_core>;
782 operating-points-v2 = <&sbc3_dvfs_opp_table>;
787 compatible = "nvidia,tegra30-slink";
790 #address-cells = <1>;
791 #size-cells = <0>;
794 reset-names = "spi";
796 dma-names = "rx", "tx";
797 power-domains = <&pd_core>;
798 operating-points-v2 = <&sbc4_dvfs_opp_table>;
803 compatible = "nvidia,tegra30-slink";
806 #address-cells = <1>;
807 #size-cells = <0>;
810 reset-names = "spi";
812 dma-names = "rx", "tx";
813 power-domains = <&pd_core>;
814 operating-points-v2 = <&sbc5_dvfs_opp_table>;
819 compatible = "nvidia,tegra30-slink";
822 #address-cells = <1>;
823 #size-cells = <0>;
826 reset-names = "spi";
828 dma-names = "rx", "tx";
829 power-domains = <&pd_core>;
830 operating-points-v2 = <&sbc6_dvfs_opp_table>;
835 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
840 reset-names = "kbc";
845 compatible = "nvidia,tegra30-pmc";
848 clock-names = "pclk", "clk32k_in";
849 #clock-cells = <1>;
851 pd_core: core-domain {
852 #power-domain-cells = <0>;
853 operating-points-v2 = <&core_opp_table>;
861 power-domains = <&pd_core>;
862 #power-domain-cells = <0>;
869 power-domains = <&pd_core>;
870 #power-domain-cells = <0>;
882 power-domains = <&pd_core>;
883 #power-domain-cells = <0>;
890 power-domains = <&pd_core>;
891 #power-domain-cells = <0>;
898 power-domains = <&pd_core>;
899 #power-domain-cells = <0>;
912 power-domains = <&pd_core>;
913 #power-domain-cells = <0>;
918 mc: memory-controller@7000f000 {
919 compatible = "nvidia,tegra30-mc";
922 clock-names = "mc";
926 #iommu-cells = <1>;
927 #reset-cells = <1>;
928 #interconnect-cells = <1>;
931 emc: memory-controller@7000f400 {
932 compatible = "nvidia,tegra30-emc";
936 power-domains = <&pd_core>;
938 nvidia,memory-controller = <&mc>;
939 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
941 #interconnect-cells = <0>;
945 compatible = "nvidia,tegra30-efuse";
948 clock-names = "fuse";
950 reset-names = "fuse";
951 power-domains = <&pd_core>;
952 operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
956 compatible = "nvidia,tegra30-tsensor";
962 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
963 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
964 assigned-clock-rates = <500000>;
966 #thermal-sensor-cells = <1>;
970 compatible = "nvidia,tegra30-hda";
976 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
980 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
985 compatible = "nvidia,tegra30-ahub";
991 clock-names = "d_audio", "apbif";
1003 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1010 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1013 #address-cells = <1>;
1014 #size-cells = <1>;
1017 compatible = "nvidia,tegra30-i2s";
1019 nvidia,ahub-cif-ids = <4 4>;
1022 reset-names = "i2s";
1027 compatible = "nvidia,tegra30-i2s";
1029 nvidia,ahub-cif-ids = <5 5>;
1032 reset-names = "i2s";
1037 compatible = "nvidia,tegra30-i2s";
1039 nvidia,ahub-cif-ids = <6 6>;
1042 reset-names = "i2s";
1047 compatible = "nvidia,tegra30-i2s";
1049 nvidia,ahub-cif-ids = <7 7>;
1052 reset-names = "i2s";
1057 compatible = "nvidia,tegra30-i2s";
1059 nvidia,ahub-cif-ids = <8 8>;
1062 reset-names = "i2s";
1068 compatible = "nvidia,tegra30-sdhci";
1072 clock-names = "sdhci";
1074 reset-names = "sdhci";
1075 power-domains = <&pd_core>;
1076 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
1081 compatible = "nvidia,tegra30-sdhci";
1085 clock-names = "sdhci";
1087 reset-names = "sdhci";
1092 compatible = "nvidia,tegra30-sdhci";
1096 clock-names = "sdhci";
1098 reset-names = "sdhci";
1099 power-domains = <&pd_core>;
1100 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
1105 compatible = "nvidia,tegra30-sdhci";
1109 clock-names = "sdhci";
1111 reset-names = "sdhci";
1116 compatible = "nvidia,tegra30-ehci";
1122 reset-names = "usb";
1123 nvidia,needs-double-reset;
1125 power-domains = <&pd_core>;
1126 operating-points-v2 = <&usbd_dvfs_opp_table>;
1130 phy1: usb-phy@7d000000 {
1131 compatible = "nvidia,tegra30-usb-phy";
1139 clock-names = "reg", "pll_u", "utmi-pads";
1141 reset-names = "usb", "utmi-pads";
1142 #phy-cells = <0>;
1143 nvidia,hssync-start-delay = <9>;
1144 nvidia,idle-wait-delay = <17>;
1145 nvidia,elastic-limit = <16>;
1146 nvidia,term-range-adj = <6>;
1147 nvidia,xcvr-setup = <51>;
1148 nvidia,xcvr-setup-use-fuses;
1149 nvidia,xcvr-lsfslew = <1>;
1150 nvidia,xcvr-lsrslew = <1>;
1151 nvidia,xcvr-hsslew = <32>;
1152 nvidia,hssquelch-level = <2>;
1153 nvidia,hsdiscon-level = <5>;
1154 nvidia,has-utmi-pad-registers;
1160 compatible = "nvidia,tegra30-ehci";
1166 reset-names = "usb";
1168 power-domains = <&pd_core>;
1169 operating-points-v2 = <&usb2_dvfs_opp_table>;
1173 phy2: usb-phy@7d004000 {
1174 compatible = "nvidia,tegra30-usb-phy";
1182 clock-names = "reg", "pll_u", "utmi-pads";
1184 reset-names = "usb", "utmi-pads";
1185 #phy-cells = <0>;
1186 nvidia,hssync-start-delay = <9>;
1187 nvidia,idle-wait-delay = <17>;
1188 nvidia,elastic-limit = <16>;
1189 nvidia,term-range-adj = <6>;
1190 nvidia,xcvr-setup = <51>;
1191 nvidia,xcvr-setup-use-fuses;
1192 nvidia,xcvr-lsfslew = <2>;
1193 nvidia,xcvr-lsrslew = <2>;
1194 nvidia,xcvr-hsslew = <32>;
1195 nvidia,hssquelch-level = <2>;
1196 nvidia,hsdiscon-level = <5>;
1202 compatible = "nvidia,tegra30-ehci";
1208 reset-names = "usb";
1210 power-domains = <&pd_core>;
1211 operating-points-v2 = <&usb3_dvfs_opp_table>;
1215 phy3: usb-phy@7d008000 {
1216 compatible = "nvidia,tegra30-usb-phy";
1224 clock-names = "reg", "pll_u", "utmi-pads";
1226 reset-names = "usb", "utmi-pads";
1227 #phy-cells = <0>;
1228 nvidia,hssync-start-delay = <0>;
1229 nvidia,idle-wait-delay = <17>;
1230 nvidia,elastic-limit = <16>;
1231 nvidia,term-range-adj = <6>;
1232 nvidia,xcvr-setup = <51>;
1233 nvidia,xcvr-setup-use-fuses;
1234 nvidia,xcvr-lsfslew = <2>;
1235 nvidia,xcvr-lsrslew = <2>;
1236 nvidia,xcvr-hsslew = <32>;
1237 nvidia,hssquelch-level = <2>;
1238 nvidia,hsdiscon-level = <5>;
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1249 compatible = "arm,cortex-a9";
1252 #cooling-cells = <2>;
1257 compatible = "arm,cortex-a9";
1260 #cooling-cells = <2>;
1265 compatible = "arm,cortex-a9";
1268 #cooling-cells = <2>;
1273 compatible = "arm,cortex-a9";
1276 #cooling-cells = <2>;
1281 compatible = "arm,cortex-a9-pmu";
1286 interrupt-affinity = <&{/cpus/cpu@0}>,
1292 thermal-zones {
1293 tsensor0-thermal {
1294 polling-delay-passive = <1000>; /* milliseconds */
1295 polling-delay = <5000>; /* milliseconds */
1297 thermal-sensors = <&tsensor 0>;
1300 level1_trip: dvfs-alert {
1307 level2_trip: cpu-div2-throttle {
1314 level3_trip: soc-critical {
1322 cooling-maps {
1325 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1334 tsensor1-thermal {
1337 polling-delay-passive = <1000>; /* milliseconds */
1338 polling-delay = <0>; /* milliseconds */
1340 thermal-sensors = <&tsensor 1>;
1343 dvfs-alert {