Lines Matching +full:0 +full:x54040000
20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
45 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
47 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
62 pci@1,0 {
64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
65 reg = <0x000800 0 0 0 0>;
66 bus-range = <0x00 0xff>;
76 pci@2,0 {
78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
79 reg = <0x001000 0 0 0 0>;
80 bus-range = <0x00 0xff>;
90 pci@3,0 {
92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
93 reg = <0x001800 0 0 0 0>;
94 bus-range = <0x00 0xff>;
107 reg = <0x40000000 0x40000>;
110 ranges = <0 0x40000000 0x40000>;
113 reg = <0x400 0x3fc00>;
120 reg = <0x50000000 0x00024000>;
135 ranges = <0x54000000 0x54000000 0x04000000>;
139 reg = <0x54040000 0x00040000>;
154 reg = <0x54080000 0x00040000>;
169 reg = <0x540c0000 0x00040000>;
184 reg = <0x54100000 0x00040000>;
198 reg = <0x54140000 0x00040000>;
211 reg = <0x54180000 0x00040000>;
230 reg = <0x54200000 0x00040000>;
242 nvidia,head = <0>;
262 reg = <0x54240000 0x00040000>;
294 reg = <0x54280000 0x00040000>;
308 reg = <0x542c0000 0x00040000>;
318 reg = <0x54300000 0x00040000>;
331 reg = <0x54400000 0x00040000>;
345 reg = <0x50040600 0x20>;
354 reg = <0x50041000 0x1000>,
355 <0x50040100 0x0100>;
363 reg = <0x50043000 0x1000>;
372 reg = <0x60004000 0x100>,
373 <0x60004100 0x50>,
374 <0x60004200 0x50>,
375 <0x60004300 0x50>,
376 <0x60004400 0x50>;
384 reg = <0x60005000 0x400>;
385 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
396 reg = <0x60006000 0x1000>;
431 reg = <0x60007000 0x1000>;
436 reg = <0x6000a000 0x1400>;
477 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
482 reg = <0x6000c800 0x400>;
497 reg = <0x6000d000 0x1000>;
510 gpio-ranges = <&pinmux 0 0 248>;
515 reg = <0x6001a000 0x1000>, /* Syntax Engine */
516 <0x6001b000 0x1000>, /* Video Bitstream Engine */
517 <0x6001c000 0x100>, /* Macroblock Engine */
518 <0x6001c200 0x100>, /* Post-processing Engine */
519 <0x6001c400 0x100>, /* Motion Compensation Engine */
520 <0x6001c600 0x100>, /* Transform Engine */
521 <0x6001c800 0x100>, /* Pixel prediction block */
522 <0x6001ca00 0x100>, /* Video DMA */
523 <0x6001d800 0x400>; /* Video frame controls */
541 reg = <0x70000800 0x64>, /* Chip revision */
542 <0x70000008 0x04>; /* Strapping options */
547 reg = <0x70000868 0x0d4>, /* Pad control registers */
548 <0x70003000 0x3e4>; /* Mux registers */
561 reg = <0x70006000 0x40>;
574 reg = <0x70006040 0x40>;
587 reg = <0x70006200 0x100>;
600 reg = <0x70006300 0x100>;
613 reg = <0x70006400 0x100>;
626 reg = <0x70009000 0x1000>;
629 ranges = <0 0 0x48000000 0x7ffffff>;
641 reg = <0x7000a000 0x100>;
653 reg = <0x7000e000 0x100>;
660 reg = <0x7000c000 0x100>;
663 #size-cells = <0>;
676 reg = <0x7000c400 0x100>;
679 #size-cells = <0>;
692 reg = <0x7000c500 0x100>;
695 #size-cells = <0>;
708 reg = <0x7000c700 0x100>;
711 #size-cells = <0>;
724 reg = <0x7000d000 0x100>;
727 #size-cells = <0>;
740 reg = <0x7000d400 0x200>;
743 #size-cells = <0>;
756 reg = <0x7000d600 0x200>;
759 #size-cells = <0>;
772 reg = <0x7000d800 0x200>;
775 #size-cells = <0>;
788 reg = <0x7000da00 0x200>;
791 #size-cells = <0>;
804 reg = <0x7000dc00 0x200>;
807 #size-cells = <0>;
820 reg = <0x7000de00 0x200>;
823 #size-cells = <0>;
836 reg = <0x7000e200 0x100>;
846 reg = <0x7000e400 0x400>;
852 #power-domain-cells = <0>;
862 #power-domain-cells = <0>;
870 #power-domain-cells = <0>;
883 #power-domain-cells = <0>;
891 #power-domain-cells = <0>;
899 #power-domain-cells = <0>;
913 #power-domain-cells = <0>;
920 reg = <0x7000f000 0x400>;
933 reg = <0x7000f400 0x400>;
941 #interconnect-cells = <0>;
946 reg = <0x7000f800 0x400>;
957 reg = <0x70014000 0x500>;
971 reg = <0x70030000 0x10000>;
986 reg = <0x70080000 0x200>,
987 <0x70080200 0x100>;
1018 reg = <0x70080300 0x100>;
1028 reg = <0x70080400 0x100>;
1038 reg = <0x70080500 0x100>;
1048 reg = <0x70080600 0x100>;
1058 reg = <0x70080700 0x100>;
1069 reg = <0x78000000 0x200>;
1082 reg = <0x78000200 0x200>;
1093 reg = <0x78000400 0x200>;
1106 reg = <0x78000600 0x200>;
1117 reg = <0x7d000000 0x4000>;
1132 reg = <0x7d000000 0x4000>,
1133 <0x7d000000 0x4000>;
1142 #phy-cells = <0>;
1155 nvidia,pmc = <&tegra_pmc 0>;
1161 reg = <0x7d004000 0x4000>;
1175 reg = <0x7d004000 0x4000>,
1176 <0x7d000000 0x4000>;
1185 #phy-cells = <0>;
1203 reg = <0x7d008000 0x4000>;
1217 reg = <0x7d008000 0x4000>,
1218 <0x7d000000 0x4000>;
1227 #phy-cells = <0>;
1228 nvidia,hssync-start-delay = <0>;
1245 #size-cells = <0>;
1247 cpu0: cpu@0 {
1250 reg = <0>;
1286 interrupt-affinity = <&{/cpus/cpu@0}>,
1297 thermal-sensors = <&tsensor 0>;
1338 polling-delay = <0>; /* milliseconds */