Lines Matching +full:xcvr +full:- +full:lsfslew
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
13 interrupt-parent = <&lic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
23 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
36 compatible = "nvidia,tegra20-host1x";
40 interrupt-names = "syncpt", "host1x";
42 clock-names = "host1x";
44 reset-names = "host1x", "mc";
45 power-domains = <&pd_core>;
46 operating-points-v2 = <&host1x_dvfs_opp_table>;
48 #address-cells = <1>;
49 #size-cells = <1>;
54 compatible = "nvidia,tegra20-mpe";
59 reset-names = "mpe";
60 power-domains = <&pd_mpe>;
61 operating-points-v2 = <&mpe_dvfs_opp_table>;
66 compatible = "nvidia,tegra20-vi";
71 reset-names = "vi";
72 power-domains = <&pd_venc>;
73 operating-points-v2 = <&vi_dvfs_opp_table>;
78 compatible = "nvidia,tegra20-epp";
83 reset-names = "epp";
84 power-domains = <&pd_core>;
85 operating-points-v2 = <&epp_dvfs_opp_table>;
90 compatible = "nvidia,tegra20-isp";
95 reset-names = "isp";
96 power-domains = <&pd_venc>;
101 compatible = "nvidia,tegra20-gr2d";
106 reset-names = "2d", "mc";
107 power-domains = <&pd_core>;
108 operating-points-v2 = <&gr2d_dvfs_opp_table>;
112 compatible = "nvidia,tegra20-gr3d";
116 reset-names = "3d", "mc";
117 power-domains = <&pd_3d>;
118 operating-points-v2 = <&gr3d_dvfs_opp_table>;
122 compatible = "nvidia,tegra20-dc";
127 clock-names = "dc", "parent";
129 reset-names = "dc";
130 power-domains = <&pd_core>;
131 operating-points-v2 = <&disp1_dvfs_opp_table>;
140 interconnect-names = "wina",
142 "winb-vfilter",
152 compatible = "nvidia,tegra20-dc";
157 clock-names = "dc", "parent";
159 reset-names = "dc";
160 power-domains = <&pd_core>;
161 operating-points-v2 = <&disp2_dvfs_opp_table>;
170 interconnect-names = "wina",
172 "winb-vfilter",
182 compatible = "nvidia,tegra20-hdmi";
187 clock-names = "hdmi", "parent";
189 reset-names = "hdmi";
190 power-domains = <&pd_core>;
191 operating-points-v2 = <&hdmi_dvfs_opp_table>;
192 #sound-dai-cells = <0>;
197 compatible = "nvidia,tegra20-tvo";
201 power-domains = <&pd_core>;
202 operating-points-v2 = <&tvo_dvfs_opp_table>;
207 compatible = "nvidia,tegra20-dsi";
211 clock-names = "dsi", "parent";
213 reset-names = "dsi";
214 power-domains = <&pd_core>;
215 operating-points-v2 = <&dsi_dvfs_opp_table>;
221 compatible = "arm,cortex-a9-twd-timer";
222 interrupt-parent = <&intc>;
229 intc: interrupt-controller@50041000 {
230 compatible = "arm,cortex-a9-gic";
233 interrupt-controller;
234 #interrupt-cells = <3>;
235 interrupt-parent = <&intc>;
238 cache-controller@50043000 {
239 compatible = "arm,pl310-cache";
241 arm,data-latency = <5 5 2>;
242 arm,tag-latency = <4 4 2>;
243 cache-unified;
244 cache-level = <2>;
247 lic: interrupt-controller@60004000 {
248 compatible = "nvidia,tegra20-ictlr";
253 interrupt-controller;
254 #interrupt-cells = <3>;
255 interrupt-parent = <&intc>;
259 compatible = "nvidia,tegra20-timer";
269 compatible = "nvidia,tegra20-car";
271 #clock-cells = <1>;
272 #reset-cells = <1>;
275 compatible = "nvidia,tegra20-sclk";
277 power-domains = <&pd_core>;
278 operating-points-v2 = <&sclk_dvfs_opp_table>;
282 flow-controller@60007000 {
283 compatible = "nvidia,tegra20-flowctrl";
288 compatible = "nvidia,tegra20-apbdma";
308 reset-names = "dma";
309 #dma-cells = <1>;
313 compatible = "nvidia,tegra20-ahb";
318 compatible = "nvidia,tegra20-gpio";
327 #gpio-cells = <2>;
328 gpio-controller;
329 #interrupt-cells = <2>;
330 interrupt-controller;
331 gpio-ranges = <&pinmux 0 0 224>;
335 compatible = "nvidia,tegra20-vde";
339 <0x6001c200 0x100>, /* Post-processing Engine */
345 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
349 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
351 interrupt-names = "sync-token", "bsev", "sxe";
353 reset-names = "vde", "mc";
355 power-domains = <&pd_vde>;
356 operating-points-v2 = <&vde_dvfs_opp_table>;
360 compatible = "nvidia,tegra20-apbmisc";
366 compatible = "nvidia,tegra20-pinmux";
367 reg = <0x70000014 0x10>, /* Tri-state registers */
369 <0x700000a0 0x14>, /* Pull-up/down registers */
374 compatible = "nvidia,tegra20-das";
379 compatible = "nvidia,tegra20-ac97";
384 reset-names = "ac97";
386 dma-names = "rx", "tx";
391 compatible = "nvidia,tegra20-spdif";
396 clock-names = "out", "in";
399 dma-names = "rx", "tx";
400 #sound-dai-cells = <0>;
403 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>;
404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
408 compatible = "nvidia,tegra20-i2s";
413 reset-names = "i2s";
415 dma-names = "rx", "tx";
420 compatible = "nvidia,tegra20-i2s";
425 reset-names = "i2s";
427 dma-names = "rx", "tx";
435 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
436 * driver, the compatible is "nvidia,tegra20-hsuart".
439 compatible = "nvidia,tegra20-uart";
441 reg-shift = <2>;
445 reset-names = "serial";
447 dma-names = "rx", "tx";
452 compatible = "nvidia,tegra20-uart";
454 reg-shift = <2>;
458 reset-names = "serial";
460 dma-names = "rx", "tx";
465 compatible = "nvidia,tegra20-uart";
467 reg-shift = <2>;
471 reset-names = "serial";
473 dma-names = "rx", "tx";
478 compatible = "nvidia,tegra20-uart";
480 reg-shift = <2>;
484 reset-names = "serial";
486 dma-names = "rx", "tx";
491 compatible = "nvidia,tegra20-uart";
493 reg-shift = <2>;
497 reset-names = "serial";
499 dma-names = "rx", "tx";
503 nand-controller@70008000 {
504 compatible = "nvidia,tegra20-nand";
506 #address-cells = <1>;
507 #size-cells = <0>;
510 clock-names = "nand";
512 reset-names = "nand";
513 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
514 assigned-clock-rates = <150000000>;
515 power-domains = <&pd_core>;
516 operating-points-v2 = <&ndflash_dvfs_opp_table>;
521 compatible = "nvidia,tegra20-gmi";
523 #address-cells = <2>;
524 #size-cells = <1>;
527 clock-names = "gmi";
529 reset-names = "gmi";
530 power-domains = <&pd_core>;
531 operating-points-v2 = <&nor_dvfs_opp_table>;
536 compatible = "nvidia,tegra20-pwm";
538 #pwm-cells = <2>;
541 reset-names = "pwm";
546 compatible = "nvidia,tegra20-rtc";
553 compatible = "nvidia,tegra20-i2c";
556 #address-cells = <1>;
557 #size-cells = <0>;
560 clock-names = "div-clk", "fast-clk";
562 reset-names = "i2c";
564 dma-names = "rx", "tx";
569 compatible = "nvidia,tegra20-sflash";
572 #address-cells = <1>;
573 #size-cells = <0>;
576 reset-names = "spi";
578 dma-names = "rx", "tx";
583 compatible = "nvidia,tegra20-i2c";
586 #address-cells = <1>;
587 #size-cells = <0>;
590 clock-names = "div-clk", "fast-clk";
592 reset-names = "i2c";
594 dma-names = "rx", "tx";
599 compatible = "nvidia,tegra20-i2c";
602 #address-cells = <1>;
603 #size-cells = <0>;
606 clock-names = "div-clk", "fast-clk";
608 reset-names = "i2c";
610 dma-names = "rx", "tx";
615 compatible = "nvidia,tegra20-i2c-dvc";
618 #address-cells = <1>;
619 #size-cells = <0>;
622 clock-names = "div-clk", "fast-clk";
624 reset-names = "i2c";
626 dma-names = "rx", "tx";
631 compatible = "nvidia,tegra20-slink";
634 #address-cells = <1>;
635 #size-cells = <0>;
638 reset-names = "spi";
640 dma-names = "rx", "tx";
645 compatible = "nvidia,tegra20-slink";
648 #address-cells = <1>;
649 #size-cells = <0>;
652 reset-names = "spi";
654 dma-names = "rx", "tx";
659 compatible = "nvidia,tegra20-slink";
662 #address-cells = <1>;
663 #size-cells = <0>;
666 reset-names = "spi";
668 dma-names = "rx", "tx";
673 compatible = "nvidia,tegra20-slink";
676 #address-cells = <1>;
677 #size-cells = <0>;
680 reset-names = "spi";
682 dma-names = "rx", "tx";
687 compatible = "nvidia,tegra20-kbc";
692 reset-names = "kbc";
697 compatible = "nvidia,tegra20-pmc";
700 clock-names = "pclk", "clk32k_in";
701 #clock-cells = <1>;
703 pd_core: core-domain {
704 #power-domain-cells = <0>;
705 operating-points-v2 = <&core_opp_table>;
713 power-domains = <&pd_core>;
714 #power-domain-cells = <0>;
726 power-domains = <&pd_core>;
727 #power-domain-cells = <0>;
734 power-domains = <&pd_core>;
735 #power-domain-cells = <0>;
744 power-domains = <&pd_core>;
745 #power-domain-cells = <0>;
750 mc: memory-controller@7000f000 {
751 compatible = "nvidia,tegra20-mc-gart";
755 clock-names = "mc";
757 #reset-cells = <1>;
758 #iommu-cells = <0>;
759 #interconnect-cells = <1>;
762 emc: memory-controller@7000f400 {
763 compatible = "nvidia,tegra20-emc";
767 power-domains = <&pd_core>;
768 #address-cells = <1>;
769 #size-cells = <0>;
770 #interconnect-cells = <0>;
772 nvidia,memory-controller = <&mc>;
773 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
777 compatible = "nvidia,tegra20-efuse";
780 clock-names = "fuse";
782 reset-names = "fuse";
786 compatible = "nvidia,tegra20-pcie";
791 reg-names = "pads", "afi", "cs";
794 interrupt-names = "intr", "msi";
796 #interrupt-cells = <1>;
797 interrupt-map-mask = <0 0 0 0>;
798 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
800 bus-range = <0x00 0xff>;
801 #address-cells = <3>;
802 #size-cells = <2>;
807 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
813 clock-names = "pex", "afi", "pll_e";
817 reset-names = "pex", "afi", "pcie_x";
818 power-domains = <&pd_core>;
819 operating-points-v2 = <&pcie_dvfs_opp_table>;
825 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
827 bus-range = <0x00 0xff>;
830 #address-cells = <3>;
831 #size-cells = <2>;
834 nvidia,num-lanes = <2>;
839 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
841 bus-range = <0x00 0xff>;
844 #address-cells = <3>;
845 #size-cells = <2>;
848 nvidia,num-lanes = <2>;
853 compatible = "nvidia,tegra20-ehci";
859 reset-names = "usb";
860 nvidia,needs-double-reset;
862 power-domains = <&pd_core>;
863 operating-points-v2 = <&usbd_dvfs_opp_table>;
867 phy1: usb-phy@c5000000 {
868 compatible = "nvidia,tegra20-usb-phy";
877 clock-names = "reg", "pll_u", "timer", "utmi-pads";
879 reset-names = "usb", "utmi-pads";
880 #phy-cells = <0>;
881 nvidia,has-legacy-mode;
882 nvidia,hssync-start-delay = <9>;
883 nvidia,idle-wait-delay = <17>;
884 nvidia,elastic-limit = <16>;
885 nvidia,term-range-adj = <6>;
886 nvidia,xcvr-setup = <9>;
887 nvidia,xcvr-lsfslew = <1>;
888 nvidia,xcvr-lsrslew = <1>;
889 nvidia,has-utmi-pad-registers;
895 compatible = "nvidia,tegra20-ehci";
901 reset-names = "usb";
903 power-domains = <&pd_core>;
904 operating-points-v2 = <&usb2_dvfs_opp_table>;
908 phy2: usb-phy@c5004000 {
909 compatible = "nvidia,tegra20-usb-phy";
916 clock-names = "reg", "pll_u", "ulpi-link";
918 reset-names = "usb", "utmi-pads";
919 #phy-cells = <0>;
925 compatible = "nvidia,tegra20-ehci";
931 reset-names = "usb";
933 power-domains = <&pd_core>;
934 operating-points-v2 = <&usb3_dvfs_opp_table>;
938 phy3: usb-phy@c5008000 {
939 compatible = "nvidia,tegra20-usb-phy";
948 clock-names = "reg", "pll_u", "timer", "utmi-pads";
950 reset-names = "usb", "utmi-pads";
951 #phy-cells = <0>;
952 nvidia,hssync-start-delay = <9>;
953 nvidia,idle-wait-delay = <17>;
954 nvidia,elastic-limit = <16>;
955 nvidia,term-range-adj = <6>;
956 nvidia,xcvr-setup = <9>;
957 nvidia,xcvr-lsfslew = <2>;
958 nvidia,xcvr-lsrslew = <2>;
964 compatible = "nvidia,tegra20-sdhci";
968 clock-names = "sdhci";
970 reset-names = "sdhci";
971 power-domains = <&pd_core>;
972 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
977 compatible = "nvidia,tegra20-sdhci";
981 clock-names = "sdhci";
983 reset-names = "sdhci";
984 power-domains = <&pd_core>;
985 operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
990 compatible = "nvidia,tegra20-sdhci";
994 clock-names = "sdhci";
996 reset-names = "sdhci";
997 power-domains = <&pd_core>;
998 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
1003 compatible = "nvidia,tegra20-sdhci";
1007 clock-names = "sdhci";
1009 reset-names = "sdhci";
1010 power-domains = <&pd_core>;
1011 operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1021 compatible = "arm,cortex-a9";
1028 compatible = "arm,cortex-a9";
1035 compatible = "arm,cortex-a9-pmu";
1038 interrupt-affinity = <&{/cpus/cpu@0}>,
1042 sound-hdmi {
1043 compatible = "simple-audio-card";
1044 simple-audio-card,name = "NVIDIA Tegra20 HDMI";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1049 simple-audio-card,dai-link@0 {
1053 sound-dai = <&tegra_spdif>;
1057 sound-dai = <&tegra_hdmi>;