Lines Matching +full:0 +full:x54140000
17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
91 reg = <0x54100000 0x00040000>;
102 reg = <0x54140000 0x00040000>;
113 reg = <0x54180000 0x00040000>;
123 reg = <0x54200000 0x00040000>;
133 nvidia,head = <0>;
153 reg = <0x54240000 0x00040000>;
183 reg = <0x54280000 0x00040000>;
192 #sound-dai-cells = <0>;
198 reg = <0x542c0000 0x00040000>;
208 reg = <0x54300000 0x00040000>;
223 reg = <0x50040600 0x20>;
231 reg = <0x50041000 0x1000>,
232 <0x50040100 0x0100>;
240 reg = <0x50043000 0x1000>;
249 reg = <0x60004000 0x100>,
250 <0x60004100 0x50>,
251 <0x60004200 0x50>,
252 <0x60004300 0x50>;
260 reg = <0x60005000 0x60>;
261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
270 reg = <0x60006000 0x1000>;
284 reg = <0x60007000 0x1000>;
289 reg = <0x6000a000 0x1200>;
314 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
319 reg = <0x6000d000 0x1000>;
331 gpio-ranges = <&pinmux 0 0 224>;
336 reg = <0x6001a000 0x1000>, /* Syntax Engine */
337 <0x6001b000 0x1000>, /* Video Bitstream Engine */
338 <0x6001c000 0x100>, /* Macroblock Engine */
339 <0x6001c200 0x100>, /* Post-processing Engine */
340 <0x6001c400 0x100>, /* Motion Compensation Engine */
341 <0x6001c600 0x100>, /* Transform Engine */
342 <0x6001c800 0x100>, /* Pixel prediction block */
343 <0x6001ca00 0x100>, /* Video DMA */
344 <0x6001d800 0x300>; /* Video frame controls */
361 reg = <0x70000800 0x64>, /* Chip revision */
362 <0x70000008 0x04>; /* Strapping options */
367 reg = <0x70000014 0x10>, /* Tri-state registers */
368 <0x70000080 0x20>, /* Mux registers */
369 <0x700000a0 0x14>, /* Pull-up/down registers */
370 <0x70000868 0xa8>; /* Pad control registers */
375 reg = <0x70000c00 0x80>;
380 reg = <0x70002000 0x200>;
392 reg = <0x70002400 0x200>;
400 #sound-dai-cells = <0>;
409 reg = <0x70002800 0x200>;
421 reg = <0x70002a00 0x200>;
440 reg = <0x70006000 0x40>;
453 reg = <0x70006040 0x40>;
466 reg = <0x70006200 0x100>;
479 reg = <0x70006300 0x100>;
492 reg = <0x70006400 0x100>;
505 reg = <0x70008000 0x100>;
507 #size-cells = <0>;
522 reg = <0x70009000 0x1000>;
525 ranges = <0 0 0xd0000000 0xfffffff>;
537 reg = <0x7000a000 0x100>;
547 reg = <0x7000e000 0x100>;
554 reg = <0x7000c000 0x100>;
557 #size-cells = <0>;
570 reg = <0x7000c380 0x80>;
573 #size-cells = <0>;
584 reg = <0x7000c400 0x100>;
587 #size-cells = <0>;
600 reg = <0x7000c500 0x100>;
603 #size-cells = <0>;
616 reg = <0x7000d000 0x200>;
619 #size-cells = <0>;
632 reg = <0x7000d400 0x200>;
635 #size-cells = <0>;
646 reg = <0x7000d600 0x200>;
649 #size-cells = <0>;
660 reg = <0x7000d800 0x200>;
663 #size-cells = <0>;
674 reg = <0x7000da00 0x200>;
677 #size-cells = <0>;
688 reg = <0x7000e200 0x100>;
698 reg = <0x7000e400 0x400>;
704 #power-domain-cells = <0>;
714 #power-domain-cells = <0>;
727 #power-domain-cells = <0>;
735 #power-domain-cells = <0>;
745 #power-domain-cells = <0>;
752 reg = <0x7000f000 0x00000400>, /* controller registers */
753 <0x58000000 0x02000000>; /* GART aperture */
758 #iommu-cells = <0>;
764 reg = <0x7000f400 0x400>;
769 #size-cells = <0>;
770 #interconnect-cells = <0>;
778 reg = <0x7000f800 0x400>;
788 reg = <0x80003000 0x00000800>, /* PADS registers */
789 <0x80003800 0x00000200>, /* AFI registers */
790 <0x90000000 0x10000000>; /* configuration space */
797 interrupt-map-mask = <0 0 0 0>;
798 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
800 bus-range = <0x00 0xff>;
804 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
805 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
806 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
807 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
808 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
823 pci@1,0 {
825 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
826 reg = <0x000800 0 0 0 0>;
827 bus-range = <0x00 0xff>;
837 pci@2,0 {
839 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
840 reg = <0x001000 0 0 0 0>;
841 bus-range = <0x00 0xff>;
854 reg = <0xc5000000 0x4000>;
869 reg = <0xc5000000 0x4000>,
870 <0xc5000000 0x4000>;
880 #phy-cells = <0>;
890 nvidia,pmc = <&tegra_pmc 0>;
896 reg = <0xc5004000 0x4000>;
910 reg = <0xc5004000 0x4000>;
919 #phy-cells = <0>;
926 reg = <0xc5008000 0x4000>;
940 reg = <0xc5008000 0x4000>,
941 <0xc5000000 0x4000>;
951 #phy-cells = <0>;
965 reg = <0xc8000000 0x200>;
978 reg = <0xc8000200 0x200>;
991 reg = <0xc8000400 0x200>;
1004 reg = <0xc8000600 0x200>;
1017 #size-cells = <0>;
1019 cpu@0 {
1022 reg = <0>;
1038 interrupt-affinity = <&{/cpus/cpu@0}>,
1047 #size-cells = <0>;
1049 simple-audio-card,dai-link@0 {
1050 reg = <0>;