Lines Matching +full:0 +full:x7000f800
21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
60 pci@1,0 {
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
74 pci@2,0 {
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
91 reg = <0x0 0x50000000 0x0 0x00034000>;
104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
108 reg = <0x0 0x54200000 0x0 0x00040000>;
117 nvidia,head = <0>;
135 reg = <0x0 0x54240000 0x0 0x00040000>;
158 reg = <0x0 0x54280000 0x0 0x00040000>;
170 reg = <0x0 0x54340000 0x0 0x00040000>;
182 reg = <0x0 0x54540000 0x0 0x00040000>;
197 reg = <0x0 0x545c0000 0x0 0x00040000>;
208 #size-cells = <0>;
217 reg = <0x0 0x50041000 0x0 0x1000>,
218 <0x0 0x50042000 0x0 0x1000>,
219 <0x0 0x50044000 0x0 0x2000>,
220 <0x0 0x50046000 0x0 0x2000>;
228 reg = <0x0 0x57000000 0x0 0x01000000>,
229 <0x0 0x58000000 0x0 0x01000000>;
246 reg = <0x0 0x60004000 0x0 0x100>,
247 <0x0 0x60004100 0x0 0x100>,
248 <0x0 0x60004200 0x0 0x100>,
249 <0x0 0x60004300 0x0 0x100>,
250 <0x0 0x60004400 0x0 0x100>;
258 reg = <0x0 0x60005000 0x0 0x400>;
259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
270 reg = <0x0 0x60006000 0x0 0x1000>;
278 reg = <0x0 0x60007000 0x0 0x1000>;
283 reg = <0x0 0x6000c800 0x0 0x400>;
298 reg = <0x0 0x6000d000 0x0 0x1000>;
311 gpio-ranges = <&pinmux 0 0 251>;
316 reg = <0x0 0x60020000 0x0 0x1400>;
357 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
358 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
363 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
364 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
365 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
378 reg = <0x0 0x70006000 0x0 0x40>;
391 reg = <0x0 0x70006040 0x0 0x40>;
404 reg = <0x0 0x70006200 0x0 0x40>;
417 reg = <0x0 0x70006300 0x0 0x40>;
430 reg = <0x0 0x7000a000 0x0 0x100>;
440 reg = <0x0 0x7000c000 0x0 0x100>;
443 #size-cells = <0>;
455 reg = <0x0 0x7000c400 0x0 0x100>;
458 #size-cells = <0>;
470 reg = <0x0 0x7000c500 0x0 0x100>;
473 #size-cells = <0>;
485 reg = <0x0 0x7000c700 0x0 0x100>;
488 #size-cells = <0>;
500 reg = <0x0 0x7000d000 0x0 0x100>;
503 #size-cells = <0>;
515 reg = <0x0 0x7000d100 0x0 0x100>;
518 #size-cells = <0>;
530 reg = <0x0 0x7000d400 0x0 0x200>;
533 #size-cells = <0>;
545 reg = <0x0 0x7000d600 0x0 0x200>;
548 #size-cells = <0>;
560 reg = <0x0 0x7000d800 0x0 0x200>;
563 #size-cells = <0>;
575 reg = <0x0 0x7000da00 0x0 0x200>;
578 #size-cells = <0>;
590 reg = <0x0 0x7000dc00 0x0 0x200>;
593 #size-cells = <0>;
605 reg = <0x0 0x7000de00 0x0 0x200>;
608 #size-cells = <0>;
620 reg = <0x0 0x7000e000 0x0 0x100>;
627 reg = <0x0 0x7000e400 0x0 0x400>;
635 reg = <0x0 0x7000f800 0x0 0x400>;
644 reg = <0x0 0x70019000 0x0 0x1000>;
657 reg = <0x0 0x7001b000 0x0 0x1000>;
664 #interconnect-cells = <0>;
669 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
670 <0x0 0x70020000 0x0 0x7000>; /* SATA */
684 reg = <0x0 0x70030000 0x0 0x10000>;
699 reg = <0x0 0x70090000 0x0 0x8000>,
700 <0x0 0x70098000 0x0 0x1000>,
701 <0x0 0x70099000 0x0 0x1000>;
734 reg = <0x0 0x7009f000 0x0 0x1000>;
743 usb2-0 {
745 #phy-cells = <0>;
750 #phy-cells = <0>;
755 #phy-cells = <0>;
764 ulpi-0 {
766 #phy-cells = <0>;
775 hsic-0 {
777 #phy-cells = <0>;
782 #phy-cells = <0>;
791 pcie-0 {
793 #phy-cells = <0>;
798 #phy-cells = <0>;
803 #phy-cells = <0>;
808 #phy-cells = <0>;
813 #phy-cells = <0>;
822 sata-0 {
824 #phy-cells = <0>;
831 usb2-0 {
843 ulpi-0 {
847 hsic-0 {
855 usb3-0 {
867 reg = <0x0 0x700b0000 0x0 0x200>;
878 reg = <0x0 0x700b0200 0x0 0x200>;
889 reg = <0x0 0x700b0400 0x0 0x200>;
900 reg = <0x0 0x700b0600 0x0 0x200>;
911 reg = <0x0 0x70015000 0x0 0x00001000>;
921 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
922 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
947 reg = <0 0x70110000 0 0x100>, /* DFLL control */
948 <0 0x70110000 0 0x100>, /* I2C output control */
949 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
950 <0 0x70110200 0 0x100>; /* Look-up table RAM */
958 #clock-cells = <0>;
961 nvidia,droop-ctrl = <0x00000f00>;
964 nvidia,ci = <0>;
971 reg = <0x0 0x70300000 0x0 0x200>,
972 <0x0 0x70300800 0x0 0x800>,
973 <0x0 0x70300200 0x0 0x600>;
1023 reg = <0x0 0x70301000 0x0 0x100>;
1033 reg = <0x0 0x70301100 0x0 0x100>;
1043 reg = <0x0 0x70301200 0x0 0x100>;
1053 reg = <0x0 0x70301300 0x0 0x100>;
1063 reg = <0x0 0x70301400 0x0 0x100>;
1074 reg = <0x0 0x7d000000 0x0 0x4000>;
1086 reg = <0x0 0x7d000000 0x0 0x4000>,
1087 <0x0 0x7d000000 0x0 0x4000>;
1096 #phy-cells = <0>;
1097 nvidia,hssync-start-delay = <0>;
1102 nvidia,xcvr-lsfslew = <0>;
1108 nvidia,pmc = <&tegra_pmc 0>;
1114 reg = <0x0 0x7d004000 0x0 0x4000>;
1126 reg = <0x0 0x7d004000 0x0 0x4000>,
1127 <0x0 0x7d000000 0x0 0x4000>;
1136 #phy-cells = <0>;
1137 nvidia,hssync-start-delay = <0>;
1142 nvidia,xcvr-lsfslew = <0>;
1153 reg = <0x0 0x7d008000 0x0 0x4000>;
1165 reg = <0x0 0x7d008000 0x0 0x4000>,
1166 <0x0 0x7d000000 0x0 0x4000>;
1175 #phy-cells = <0>;
1176 nvidia,hssync-start-delay = <0>;
1181 nvidia,xcvr-lsfslew = <0>;
1192 #size-cells = <0>;
1194 cpu@0 {
1197 reg = <0>;
1234 interrupt-affinity = <&{/cpus/cpu@0}>,
1251 hysteresis = <0>;
1279 hysteresis = <0>;
1307 hysteresis = <0>;
1335 hysteresis = <0>;