Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
17 reg = <0x80000000 0x0>;
21 compatible = "mmio-sram";
22 reg = <0x40000000 0x40000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
28 reg = <0x400 0x3fc00>;
34 compatible = "nvidia,tegra114-host1x";
35 reg = <0x50000000 0x00028000>;
38 interrupt-names = "syncpt", "host1x";
40 clock-names = "host1x";
42 reset-names = "host1x", "mc";
45 #address-cells = <1>;
46 #size-cells = <1>;
51 compatible = "nvidia,tegra114-gr2d";
52 reg = <0x54140000 0x00040000>;
56 reset-names = "2d", "mc";
62 compatible = "nvidia,tegra114-gr3d";
63 reg = <0x54180000 0x00040000>;
66 reset-names = "3d", "mc";
72 compatible = "nvidia,tegra114-dc";
73 reg = <0x54200000 0x00040000>;
77 clock-names = "dc", "parent";
79 reset-names = "dc";
91 compatible = "nvidia,tegra114-dc";
92 reg = <0x54240000 0x00040000>;
96 clock-names = "dc", "parent";
98 reset-names = "dc";
110 compatible = "nvidia,tegra114-hdmi";
111 reg = <0x54280000 0x00040000>;
115 clock-names = "hdmi", "parent";
117 reset-names = "hdmi";
122 compatible = "nvidia,tegra114-dsi";
123 reg = <0x54300000 0x00040000>;
127 clock-names = "dsi", "lp", "parent";
129 reset-names = "dsi";
130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
133 #address-cells = <1>;
134 #size-cells = <0>;
138 compatible = "nvidia,tegra114-dsi";
139 reg = <0x54400000 0x00040000>;
143 clock-names = "dsi", "lp", "parent";
145 reset-names = "dsi";
146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
149 #address-cells = <1>;
150 #size-cells = <0>;
154 gic: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a15-gic";
156 #interrupt-cells = <3>;
157 interrupt-controller;
158 reg = <0x50041000 0x1000>,
164 interrupt-parent = <&gic>;
167 lic: interrupt-controller@60004000 {
168 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
169 reg = <0x60004000 0x100>,
174 interrupt-controller;
175 #interrupt-cells = <3>;
176 interrupt-parent = <&gic>;
180 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
181 reg = <0x60005000 0x400>;
192 compatible = "nvidia,tegra114-car";
193 reg = <0x60006000 0x1000>;
194 #clock-cells = <1>;
195 #reset-cells = <1>;
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra114-flowctrl";
200 reg = <0x60007000 0x1000>;
204 compatible = "nvidia,tegra114-apbdma";
205 reg = <0x6000a000 0x1400>;
240 reset-names = "dma";
241 #dma-cells = <1>;
245 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
246 reg = <0x6000c000 0x150>;
250 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
251 reg = <0x6000d000 0x1000>;
260 #gpio-cells = <2>;
261 gpio-controller;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 gpio-ranges = <&pinmux 0 0 246>;
268 compatible = "nvidia,tegra114-vde";
269 reg = <0x6001a000 0x1000>, /* Syntax Engine */
272 <0x6001c200 0x100>, /* Post-processing Engine */
278 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
282 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
284 interrupt-names = "sync-token", "bsev", "sxe";
286 reset-names = "vde", "mc";
292 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
293 reg = <0x70000800 0x64>, /* Chip revision */
298 compatible = "nvidia,tegra114-pinmux";
299 reg = <0x70000868 0x148>, /* Pad control registers */
307 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
309 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
312 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
313 reg = <0x70006000 0x40>;
314 reg-shift = <2>;
318 reset-names = "serial";
320 dma-names = "rx", "tx";
325 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
326 reg = <0x70006040 0x40>;
327 reg-shift = <2>;
331 reset-names = "serial";
333 dma-names = "rx", "tx";
338 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
339 reg = <0x70006200 0x100>;
340 reg-shift = <2>;
344 reset-names = "serial";
346 dma-names = "rx", "tx";
351 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
352 reg = <0x70006300 0x100>;
353 reg-shift = <2>;
357 reset-names = "serial";
359 dma-names = "rx", "tx";
364 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
365 reg = <0x7000a000 0x100>;
366 #pwm-cells = <2>;
369 reset-names = "pwm";
374 compatible = "nvidia,tegra114-i2c";
375 reg = <0x7000c000 0x100>;
377 #address-cells = <1>;
378 #size-cells = <0>;
380 clock-names = "div-clk";
382 reset-names = "i2c";
384 dma-names = "rx", "tx";
389 compatible = "nvidia,tegra114-i2c";
390 reg = <0x7000c400 0x100>;
392 #address-cells = <1>;
393 #size-cells = <0>;
395 clock-names = "div-clk";
397 reset-names = "i2c";
399 dma-names = "rx", "tx";
404 compatible = "nvidia,tegra114-i2c";
405 reg = <0x7000c500 0x100>;
407 #address-cells = <1>;
408 #size-cells = <0>;
410 clock-names = "div-clk";
412 reset-names = "i2c";
414 dma-names = "rx", "tx";
419 compatible = "nvidia,tegra114-i2c";
420 reg = <0x7000c700 0x100>;
422 #address-cells = <1>;
423 #size-cells = <0>;
425 clock-names = "div-clk";
427 reset-names = "i2c";
429 dma-names = "rx", "tx";
434 compatible = "nvidia,tegra114-i2c";
435 reg = <0x7000d000 0x100>;
437 #address-cells = <1>;
438 #size-cells = <0>;
440 clock-names = "div-clk";
442 reset-names = "i2c";
444 dma-names = "rx", "tx";
449 compatible = "nvidia,tegra114-spi";
450 reg = <0x7000d400 0x200>;
452 #address-cells = <1>;
453 #size-cells = <0>;
455 clock-names = "spi";
457 reset-names = "spi";
459 dma-names = "rx", "tx";
464 compatible = "nvidia,tegra114-spi";
465 reg = <0x7000d600 0x200>;
467 #address-cells = <1>;
468 #size-cells = <0>;
470 clock-names = "spi";
472 reset-names = "spi";
474 dma-names = "rx", "tx";
479 compatible = "nvidia,tegra114-spi";
480 reg = <0x7000d800 0x200>;
482 #address-cells = <1>;
483 #size-cells = <0>;
485 clock-names = "spi";
487 reset-names = "spi";
489 dma-names = "rx", "tx";
494 compatible = "nvidia,tegra114-spi";
495 reg = <0x7000da00 0x200>;
497 #address-cells = <1>;
498 #size-cells = <0>;
500 clock-names = "spi";
502 reset-names = "spi";
504 dma-names = "rx", "tx";
509 compatible = "nvidia,tegra114-spi";
510 reg = <0x7000dc00 0x200>;
512 #address-cells = <1>;
513 #size-cells = <0>;
515 clock-names = "spi";
517 reset-names = "spi";
519 dma-names = "rx", "tx";
524 compatible = "nvidia,tegra114-spi";
525 reg = <0x7000de00 0x200>;
527 #address-cells = <1>;
528 #size-cells = <0>;
530 clock-names = "spi";
532 reset-names = "spi";
534 dma-names = "rx", "tx";
539 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
540 reg = <0x7000e000 0x100>;
546 compatible = "nvidia,tegra114-kbc";
547 reg = <0x7000e200 0x100>;
551 reset-names = "kbc";
556 compatible = "nvidia,tegra114-pmc";
557 reg = <0x7000e400 0x400>;
559 clock-names = "pclk", "clk32k_in";
560 #clock-cells = <1>;
564 compatible = "nvidia,tegra114-efuse";
565 reg = <0x7000f800 0x400>;
567 clock-names = "fuse";
569 reset-names = "fuse";
572 mc: memory-controller@70019000 {
573 compatible = "nvidia,tegra114-mc";
574 reg = <0x70019000 0x1000>;
576 clock-names = "mc";
580 #reset-cells = <1>;
581 #iommu-cells = <1>;
585 compatible = "nvidia,tegra114-ahub";
586 reg = <0x70080000 0x200>,
592 clock-names = "d_audio", "apbif";
606 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
619 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
624 #address-cells = <1>;
625 #size-cells = <1>;
628 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
629 reg = <0x70080300 0x100>;
630 nvidia,ahub-cif-ids = <4 4>;
633 reset-names = "i2s";
638 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
639 reg = <0x70080400 0x100>;
640 nvidia,ahub-cif-ids = <5 5>;
643 reset-names = "i2s";
648 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
649 reg = <0x70080500 0x100>;
650 nvidia,ahub-cif-ids = <6 6>;
653 reset-names = "i2s";
658 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
659 reg = <0x70080600 0x100>;
660 nvidia,ahub-cif-ids = <7 7>;
663 reset-names = "i2s";
668 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
669 reg = <0x70080700 0x100>;
670 nvidia,ahub-cif-ids = <8 8>;
673 reset-names = "i2s";
679 compatible = "nvidia,tegra114-mipi";
680 reg = <0x700e3000 0x100>;
682 #nvidia,mipi-calibrate-cells = <1>;
686 compatible = "nvidia,tegra114-sdhci";
687 reg = <0x78000000 0x200>;
690 clock-names = "sdhci";
692 reset-names = "sdhci";
697 compatible = "nvidia,tegra114-sdhci";
698 reg = <0x78000200 0x200>;
701 clock-names = "sdhci";
703 reset-names = "sdhci";
708 compatible = "nvidia,tegra114-sdhci";
709 reg = <0x78000400 0x200>;
712 clock-names = "sdhci";
714 reset-names = "sdhci";
719 compatible = "nvidia,tegra114-sdhci";
720 reg = <0x78000600 0x200>;
723 clock-names = "sdhci";
725 reset-names = "sdhci";
730 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
731 reg = <0x7d000000 0x4000>;
736 reset-names = "usb";
741 phy1: usb-phy@7d000000 {
742 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
743 reg = <0x7d000000 0x4000>,
750 clock-names = "reg", "pll_u", "utmi-pads";
752 reset-names = "usb", "utmi-pads";
753 #phy-cells = <0>;
754 nvidia,hssync-start-delay = <0>;
755 nvidia,idle-wait-delay = <17>;
756 nvidia,elastic-limit = <16>;
757 nvidia,term-range-adj = <6>;
758 nvidia,xcvr-setup = <9>;
759 nvidia,xcvr-lsfslew = <0>;
760 nvidia,xcvr-lsrslew = <3>;
761 nvidia,hssquelch-level = <2>;
762 nvidia,hsdiscon-level = <5>;
763 nvidia,xcvr-hsslew = <12>;
764 nvidia,has-utmi-pad-registers;
770 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
771 reg = <0x7d008000 0x4000>;
776 reset-names = "usb";
781 phy3: usb-phy@7d008000 {
782 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
783 reg = <0x7d008000 0x4000>,
790 clock-names = "reg", "pll_u", "utmi-pads";
792 reset-names = "usb", "utmi-pads";
793 #phy-cells = <0>;
794 nvidia,hssync-start-delay = <0>;
795 nvidia,idle-wait-delay = <17>;
796 nvidia,elastic-limit = <16>;
797 nvidia,term-range-adj = <6>;
798 nvidia,xcvr-setup = <9>;
799 nvidia,xcvr-lsfslew = <0>;
800 nvidia,xcvr-lsrslew = <3>;
801 nvidia,hssquelch-level = <2>;
802 nvidia,hsdiscon-level = <5>;
803 nvidia,xcvr-hsslew = <12>;
809 #address-cells = <1>;
810 #size-cells = <0>;
814 compatible = "arm,cortex-a15";
815 reg = <0>;
820 compatible = "arm,cortex-a15";
821 reg = <1>;
826 compatible = "arm,cortex-a15";
827 reg = <2>;
832 compatible = "arm,cortex-a15";
833 reg = <3>;
838 compatible = "arm,armv7-timer";
848 interrupt-parent = <&gic>;