Lines Matching +full:mmio +full:- +full:sram
1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
20 clock-output-names = "osc24M";
23 osc32k: clk-32k {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <32768>;
27 clock-output-names = "osc32k";
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,arm926ej-s";
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
48 sram-controller@1c00000 {
49 compatible = "allwinner,suniv-f1c100s-system-control",
50 "allwinner,sun4i-a10-system-control";
52 #address-cells = <1>;
53 #size-cells = <1>;
56 sram_d: sram@10000 {
57 compatible = "mmio-sram";
59 #address-cells = <1>;
60 #size-cells = <1>;
63 otg_sram: sram-section@0 {
64 compatible = "allwinner,suniv-f1c100s-sram-d",
65 "allwinner,sun4i-a10-sram-d";
73 compatible = "allwinner,suniv-f1c100s-spi",
74 "allwinner,sun8i-h3-spi";
78 clock-names = "ahb", "mod";
81 num-cs = <1>;
82 #address-cells = <1>;
83 #size-cells = <0>;
87 compatible = "allwinner,suniv-f1c100s-spi",
88 "allwinner,sun8i-h3-spi";
92 clock-names = "ahb", "mod";
95 num-cs = <1>;
96 #address-cells = <1>;
97 #size-cells = <0>;
101 compatible = "allwinner,suniv-f1c100s-mmc",
102 "allwinner,sun7i-a20-mmc";
108 clock-names = "ahb", "mmc", "output", "sample";
110 reset-names = "ahb";
112 pinctrl-names = "default";
113 pinctrl-0 = <&mmc0_pins>;
115 #address-cells = <1>;
116 #size-cells = <0>;
120 compatible = "allwinner,suniv-f1c100s-mmc",
121 "allwinner,sun7i-a20-mmc";
127 clock-names = "ahb", "mmc", "output", "sample";
129 reset-names = "ahb";
132 #address-cells = <1>;
133 #size-cells = <0>;
137 compatible = "allwinner,suniv-f1c100s-ccu";
140 clock-names = "hosc", "losc";
141 #clock-cells = <1>;
142 #reset-cells = <1>;
145 intc: interrupt-controller@1c20400 {
146 compatible = "allwinner,suniv-f1c100s-ic";
148 interrupt-controller;
149 #interrupt-cells = <1>;
153 compatible = "allwinner,suniv-f1c100s-pinctrl";
157 clock-names = "apb", "hosc", "losc";
158 gpio-controller;
159 interrupt-controller;
160 #interrupt-cells = <3>;
161 #gpio-cells = <3>;
163 mmc0_pins: mmc0-pins {
166 drive-strength = <30>;
169 spi0_pc_pins: spi0-pc-pins {
174 uart0_pe_pins: uart0-pe-pins {
181 compatible = "allwinner,suniv-f1c100s-timer";
188 compatible = "allwinner,suniv-f1c100s-wdt",
189 "allwinner,sun6i-a31-wdt";
196 compatible = "snps,dw-apb-uart";
199 reg-shift = <2>;
200 reg-io-width = <4>;
207 compatible = "snps,dw-apb-uart";
210 reg-shift = <2>;
211 reg-io-width = <4>;
218 compatible = "snps,dw-apb-uart";
221 reg-shift = <2>;
222 reg-io-width = <4>;