Lines Matching +full:1 +full:- +full:9 +full:a +full:- +full:d
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 adc1_in6_pins_a: adc1-in6-0 {
15 adc12_ain_pins_a: adc12-ain-0 {
24 adc12_ain_pins_b: adc12-ain-1 {
31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
38 cec_pins_a: cec-0 {
40 pinmux = <STM32_PINMUX('A', 15, AF4)>;
41 bias-disable;
42 drive-open-drain;
43 slew-rate = <0>;
47 cec_sleep_pins_a: cec-sleep-0 {
49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
53 cec_pins_b: cec-1 {
56 bias-disable;
57 drive-open-drain;
58 slew-rate = <0>;
62 cec_sleep_pins_b: cec-sleep-1 {
68 dac_ch1_pins_a: dac-ch1-0 {
70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
74 dac_ch2_pins_a: dac-ch2-0 {
76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
80 dcmi_pins_a: dcmi-0 {
84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
97 bias-disable;
101 dcmi_sleep_pins_a: dcmi-sleep-0 {
105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
121 dcmi_pins_b: dcmi-1 {
123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
129 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
131 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
134 bias-disable;
138 dcmi_sleep_pins_b: dcmi-sleep-1 {
140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
146 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
148 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
154 dcmi_pins_c: dcmi-2 {
156 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
158 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
159 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
162 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
167 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
169 bias-pull-up;
173 dcmi_sleep_pins_c: dcmi-sleep-2 {
175 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
177 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
178 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
181 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
186 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
191 ethernet0_rgmii_pins_a: rgmii-0 {
200 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
201 bias-disable;
202 drive-push-pull;
203 slew-rate = <2>;
206 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
207 bias-disable;
208 drive-push-pull;
209 slew-rate = <0>;
215 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
216 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
217 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
218 bias-disable;
222 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
231 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
232 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
236 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
237 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
238 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
242 ethernet0_rgmii_pins_b: rgmii-1 {
251 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
252 bias-disable;
253 drive-push-pull;
254 slew-rate = <2>;
257 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
258 bias-disable;
259 drive-push-pull;
260 slew-rate = <0>;
267 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
268 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
269 bias-disable;
273 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
282 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
283 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
288 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
289 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
293 ethernet0_rgmii_pins_c: rgmii-2 {
302 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
303 bias-disable;
304 drive-push-pull;
305 slew-rate = <2>;
308 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
309 bias-disable;
310 drive-push-pull;
311 slew-rate = <0>;
317 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
318 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
319 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
320 bias-disable;
324 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
333 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
334 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
338 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
339 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
340 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
344 ethernet0_rmii_pins_a: rmii-0 {
349 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
350 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
351 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
352 bias-disable;
353 drive-push-pull;
354 slew-rate = <2>;
359 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
360 bias-disable;
364 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
369 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
370 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
373 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
374 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
378 ethernet0_rmii_pins_b: rmii-1 {
381 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
384 bias-disable;
385 drive-push-pull;
386 slew-rate = <1>;
389 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
390 bias-disable;
391 drive-push-pull;
392 slew-rate = <0>;
395 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
398 bias-disable;
405 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
407 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
408 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
411 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
419 ethernet0_rmii_pins_c: rmii-2 {
424 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
425 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
426 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
427 bias-disable;
428 drive-push-pull;
429 slew-rate = <2>;
434 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
435 bias-disable;
439 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
444 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
445 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
448 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
449 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
453 fmc_pins_a: fmc-0 {
455 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
456 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
457 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
458 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
459 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
460 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
461 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
462 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
465 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
467 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
468 bias-disable;
469 drive-push-pull;
470 slew-rate = <1>;
473 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
474 bias-pull-up;
478 fmc_sleep_pins_a: fmc-sleep-0 {
480 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
481 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
482 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
483 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
484 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
485 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
486 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
487 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
490 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
492 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
493 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
497 fmc_pins_b: fmc-1 {
499 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
500 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
502 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
503 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
504 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
505 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
508 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
515 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
516 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
517 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
518 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
520 bias-disable;
521 drive-push-pull;
522 slew-rate = <3>;
526 fmc_sleep_pins_b: fmc-sleep-1 {
528 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
529 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
531 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
532 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
533 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
534 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
537 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
544 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
545 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
546 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
547 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
552 i2c1_pins_a: i2c1-0 {
554 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
556 bias-disable;
557 drive-open-drain;
558 slew-rate = <0>;
562 i2c1_sleep_pins_a: i2c1-sleep-0 {
564 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
569 i2c1_pins_b: i2c1-1 {
573 bias-disable;
574 drive-open-drain;
575 slew-rate = <0>;
579 i2c1_sleep_pins_b: i2c1-sleep-1 {
586 i2c2_pins_a: i2c2-0 {
590 bias-disable;
591 drive-open-drain;
592 slew-rate = <0>;
596 i2c2_sleep_pins_a: i2c2-sleep-0 {
603 i2c2_pins_b1: i2c2-1 {
606 bias-disable;
607 drive-open-drain;
608 slew-rate = <0>;
612 i2c2_sleep_pins_b1: i2c2-sleep-1 {
618 i2c2_pins_c: i2c2-2 {
620 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
622 bias-disable;
623 drive-open-drain;
624 slew-rate = <0>;
628 i2c2_pins_sleep_c: i2c2-sleep-2 {
630 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
635 i2c5_pins_a: i2c5-0 {
637 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
638 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
639 bias-disable;
640 drive-open-drain;
641 slew-rate = <0>;
645 i2c5_sleep_pins_a: i2c5-sleep-0 {
647 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
648 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
653 i2c5_pins_b: i2c5-1 {
655 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
656 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
657 bias-disable;
658 drive-open-drain;
659 slew-rate = <0>;
663 i2c5_sleep_pins_b: i2c5-sleep-1 {
665 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
666 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
670 i2s2_pins_a: i2s2-0 {
673 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
674 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
675 slew-rate = <1>;
676 drive-push-pull;
677 bias-disable;
681 i2s2_sleep_pins_a: i2s2-sleep-0 {
684 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
685 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
689 ltdc_pins_a: ltdc-0 {
693 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
698 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
709 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
711 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
714 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
716 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
718 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
719 bias-disable;
720 drive-push-pull;
721 slew-rate = <1>;
725 ltdc_sleep_pins_a: ltdc-sleep-0 {
729 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
734 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
745 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
747 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
750 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
752 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
754 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
758 ltdc_pins_b: ltdc-1 {
766 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
774 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
778 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
788 bias-disable;
789 drive-push-pull;
790 slew-rate = <1>;
794 ltdc_sleep_pins_b: ltdc-sleep-1 {
802 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
810 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
814 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
827 ltdc_pins_c: ltdc-2 {
829 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
830 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
832 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
833 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
834 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
841 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
845 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
848 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
850 bias-disable;
851 drive-push-pull;
852 slew-rate = <0>;
856 bias-disable;
857 drive-push-pull;
858 slew-rate = <1>;
862 ltdc_sleep_pins_c: ltdc-sleep-2 {
864 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
865 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
867 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
868 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
869 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
876 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
880 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
883 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
889 ltdc_pins_d: ltdc-3 {
892 bias-disable;
893 drive-push-pull;
894 slew-rate = <3>;
898 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
903 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
904 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
916 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
919 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
921 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
924 bias-disable;
925 drive-push-pull;
926 slew-rate = <2>;
930 ltdc_sleep_pins_d: ltdc-sleep-3 {
934 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
939 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
940 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
952 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
955 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
957 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
963 mco1_pins_a: mco1-0 {
965 pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
966 bias-disable;
967 drive-push-pull;
968 slew-rate = <1>;
972 mco1_sleep_pins_a: mco1-sleep-0 {
974 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
978 mco2_pins_a: mco2-0 {
981 bias-disable;
982 drive-push-pull;
983 slew-rate = <2>;
987 mco2_sleep_pins_a: mco2-sleep-0 {
993 m_can1_pins_a: m-can1-0 {
996 slew-rate = <1>;
997 drive-push-pull;
998 bias-disable;
1001 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
1002 bias-disable;
1006 m_can1_sleep_pins_a: m_can1-sleep-0 {
1009 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
1013 m_can1_pins_b: m-can1-1 {
1015 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
1016 slew-rate = <1>;
1017 drive-push-pull;
1018 bias-disable;
1021 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
1022 bias-disable;
1026 m_can1_sleep_pins_b: m_can1-sleep-1 {
1028 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
1029 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
1033 m_can1_pins_c: m-can1-2 {
1036 slew-rate = <1>;
1037 drive-push-pull;
1038 bias-disable;
1042 bias-disable;
1046 m_can1_sleep_pins_c: m_can1-sleep-2 {
1053 m_can2_pins_a: m-can2-0 {
1056 slew-rate = <1>;
1057 drive-push-pull;
1058 bias-disable;
1062 bias-disable;
1066 m_can2_sleep_pins_a: m_can2-sleep-0 {
1073 pwm1_pins_a: pwm1-0 {
1075 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
1078 bias-pull-down;
1079 drive-push-pull;
1080 slew-rate = <0>;
1084 pwm1_sleep_pins_a: pwm1-sleep-0 {
1086 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
1092 pwm1_pins_b: pwm1-1 {
1094 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
1095 bias-pull-down;
1096 drive-push-pull;
1097 slew-rate = <0>;
1101 pwm1_sleep_pins_b: pwm1-sleep-1 {
1103 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
1107 pwm2_pins_a: pwm2-0 {
1109 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
1110 bias-pull-down;
1111 drive-push-pull;
1112 slew-rate = <0>;
1116 pwm2_sleep_pins_a: pwm2-sleep-0 {
1118 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
1122 pwm3_pins_a: pwm3-0 {
1125 bias-pull-down;
1126 drive-push-pull;
1127 slew-rate = <0>;
1131 pwm3_sleep_pins_a: pwm3-sleep-0 {
1137 pwm3_pins_b: pwm3-1 {
1140 bias-disable;
1141 drive-push-pull;
1142 slew-rate = <0>;
1146 pwm3_sleep_pins_b: pwm3-sleep-1 {
1152 pwm4_pins_a: pwm4-0 {
1154 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
1155 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
1156 bias-pull-down;
1157 drive-push-pull;
1158 slew-rate = <0>;
1162 pwm4_sleep_pins_a: pwm4-sleep-0 {
1164 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
1165 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
1169 pwm4_pins_b: pwm4-1 {
1171 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
1172 bias-pull-down;
1173 drive-push-pull;
1174 slew-rate = <0>;
1178 pwm4_sleep_pins_b: pwm4-sleep-1 {
1180 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
1184 pwm5_pins_a: pwm5-0 {
1187 bias-pull-down;
1188 drive-push-pull;
1189 slew-rate = <0>;
1193 pwm5_sleep_pins_a: pwm5-sleep-0 {
1199 pwm5_pins_b: pwm5-1 {
1204 bias-disable;
1205 drive-push-pull;
1206 slew-rate = <0>;
1210 pwm5_sleep_pins_b: pwm5-sleep-1 {
1218 pwm8_pins_a: pwm8-0 {
1221 bias-pull-down;
1222 drive-push-pull;
1223 slew-rate = <0>;
1227 pwm8_sleep_pins_a: pwm8-sleep-0 {
1233 pwm12_pins_a: pwm12-0 {
1236 bias-pull-down;
1237 drive-push-pull;
1238 slew-rate = <0>;
1242 pwm12_sleep_pins_a: pwm12-sleep-0 {
1248 qspi_clk_pins_a: qspi-clk-0 {
1251 bias-disable;
1252 drive-push-pull;
1253 slew-rate = <3>;
1257 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
1263 qspi_bk1_pins_a: qspi-bk1-0 {
1266 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
1269 bias-disable;
1270 drive-push-pull;
1271 slew-rate = <1>;
1275 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
1278 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
1284 qspi_bk2_pins_a: qspi-bk2-0 {
1290 bias-disable;
1291 drive-push-pull;
1292 slew-rate = <1>;
1296 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
1305 qspi_cs1_pins_a: qspi-cs1-0 {
1308 bias-pull-up;
1309 drive-push-pull;
1310 slew-rate = <1>;
1314 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
1320 qspi_cs2_pins_a: qspi-cs2-0 {
1323 bias-pull-up;
1324 drive-push-pull;
1325 slew-rate = <1>;
1329 qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
1335 sai2a_pins_a: sai2a-0 {
1341 slew-rate = <0>;
1342 drive-push-pull;
1343 bias-disable;
1347 sai2a_sleep_pins_a: sai2a-sleep-0 {
1356 sai2a_pins_b: sai2a-1 {
1360 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
1361 slew-rate = <0>;
1362 drive-push-pull;
1363 bias-disable;
1367 sai2a_sleep_pins_b: sai2a-sleep-1 {
1371 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
1375 sai2a_pins_c: sai2a-2 {
1377 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
1378 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
1379 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
1380 slew-rate = <0>;
1381 drive-push-pull;
1382 bias-disable;
1386 sai2a_sleep_pins_c: sai2a-sleep-2 {
1388 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
1389 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
1390 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
1394 sai2b_pins_a: sai2b-0 {
1399 slew-rate = <0>;
1400 drive-push-pull;
1401 bias-disable;
1405 bias-disable;
1409 sai2b_sleep_pins_a: sai2b-sleep-0 {
1418 sai2b_pins_b: sai2b-1 {
1421 bias-disable;
1425 sai2b_sleep_pins_b: sai2b-sleep-1 {
1431 sai2b_pins_c: sai2b-2 {
1434 bias-disable;
1438 sai2b_sleep_pins_c: sai2b-sleep-2 {
1444 sai4a_pins_a: sai4a-0 {
1447 slew-rate = <0>;
1448 drive-push-pull;
1449 bias-disable;
1453 sai4a_sleep_pins_a: sai4a-sleep-0 {
1459 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
1462 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1465 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1466 slew-rate = <1>;
1467 drive-push-pull;
1468 bias-disable;
1472 slew-rate = <2>;
1473 drive-push-pull;
1474 bias-disable;
1478 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
1481 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1484 slew-rate = <1>;
1485 drive-push-pull;
1486 bias-disable;
1490 slew-rate = <2>;
1491 drive-push-pull;
1492 bias-disable;
1495 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1496 slew-rate = <1>;
1497 drive-open-drain;
1498 bias-disable;
1502 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
1505 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1508 slew-rate = <1>;
1509 drive-push-pull;
1510 bias-disable;
1514 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
1517 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1521 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1525 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
1529 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1530 slew-rate = <1>;
1531 drive-push-pull;
1532 bias-pull-up;
1536 bias-pull-up;
1540 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
1544 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1545 slew-rate = <1>;
1546 drive-push-pull;
1547 bias-pull-up;
1551 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
1555 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1560 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
1564 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1565 slew-rate = <1>;
1566 drive-push-pull;
1567 bias-pull-up;
1571 bias-pull-up;
1575 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
1579 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1584 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
1591 slew-rate = <1>;
1592 drive-push-pull;
1593 bias-pull-up;
1597 slew-rate = <2>;
1598 drive-push-pull;
1599 bias-pull-up;
1603 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
1609 slew-rate = <1>;
1610 drive-push-pull;
1611 bias-pull-up;
1615 slew-rate = <2>;
1616 drive-push-pull;
1617 bias-pull-up;
1621 slew-rate = <1>;
1622 drive-open-drain;
1623 bias-pull-up;
1627 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
1638 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1645 slew-rate = <1>;
1646 drive-push-pull;
1647 bias-disable;
1651 slew-rate = <2>;
1652 drive-push-pull;
1653 bias-disable;
1657 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1663 slew-rate = <1>;
1664 drive-push-pull;
1665 bias-disable;
1669 slew-rate = <2>;
1670 drive-push-pull;
1671 bias-disable;
1675 slew-rate = <1>;
1676 drive-open-drain;
1677 bias-disable;
1681 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1683 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1684 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1686 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1687 slew-rate = <1>;
1688 drive-push-pull;
1689 bias-pull-up;
1693 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1695 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1696 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1698 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1702 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1704 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1705 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1708 slew-rate = <1>;
1709 drive-push-pull;
1710 bias-disable;
1714 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1716 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1717 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1723 sdmmc2_d47_pins_c: sdmmc2-d47-2 {
1725 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1726 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1729 slew-rate = <1>;
1730 drive-push-pull;
1731 bias-pull-up;
1735 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
1737 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1738 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1744 sdmmc2_d47_pins_d: sdmmc2-d47-3 {
1746 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1747 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1753 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
1755 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1756 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1762 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1767 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
1768 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
1769 slew-rate = <1>;
1770 drive-push-pull;
1771 bias-pull-up;
1775 slew-rate = <2>;
1776 drive-push-pull;
1777 bias-pull-up;
1781 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1786 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1787 slew-rate = <1>;
1788 drive-push-pull;
1789 bias-pull-up;
1793 slew-rate = <2>;
1794 drive-push-pull;
1795 bias-pull-up;
1798 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1799 slew-rate = <1>;
1800 drive-open-drain;
1801 bias-pull-up;
1805 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1810 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1812 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1816 sdmmc3_b4_pins_b: sdmmc3-b4-1 {
1820 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
1821 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
1822 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
1823 slew-rate = <1>;
1824 drive-push-pull;
1825 bias-pull-up;
1829 slew-rate = <2>;
1830 drive-push-pull;
1831 bias-pull-up;
1835 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
1839 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
1840 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1841 slew-rate = <1>;
1842 drive-push-pull;
1843 bias-pull-up;
1847 slew-rate = <2>;
1848 drive-push-pull;
1849 bias-pull-up;
1852 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
1853 slew-rate = <1>;
1854 drive-open-drain;
1855 bias-pull-up;
1859 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
1863 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
1864 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1866 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
1870 spdifrx_pins_a: spdifrx-0 {
1873 bias-disable;
1877 spdifrx_sleep_pins_a: spdifrx-sleep-0 {
1883 spi2_pins_a: spi2-0 {
1887 bias-disable;
1888 drive-push-pull;
1889 slew-rate = <1>;
1894 bias-disable;
1898 spi2_pins_b: spi2-1 {
1900 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
1902 bias-disable;
1903 drive-push-pull;
1904 slew-rate = <1>;
1909 bias-disable;
1913 spi4_pins_a: spi4-0 {
1917 bias-disable;
1918 drive-push-pull;
1919 slew-rate = <1>;
1923 bias-disable;
1927 stusb1600_pins_a: stusb1600-0 {
1930 bias-pull-up;
1934 uart4_pins_a: uart4-0 {
1937 bias-disable;
1938 drive-push-pull;
1939 slew-rate = <0>;
1943 bias-disable;
1947 uart4_idle_pins_a: uart4-idle-0 {
1953 bias-disable;
1957 uart4_sleep_pins_a: uart4-sleep-0 {
1964 uart4_pins_b: uart4-1 {
1966 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
1967 bias-disable;
1968 drive-push-pull;
1969 slew-rate = <0>;
1973 bias-disable;
1977 uart4_pins_c: uart4-2 {
1980 bias-disable;
1981 drive-push-pull;
1982 slew-rate = <0>;
1986 bias-disable;
1990 uart4_pins_d: uart4-3 {
1992 pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
1993 bias-disable;
1994 drive-push-pull;
1995 slew-rate = <0>;
1999 bias-disable;
2003 uart4_idle_pins_d: uart4-idle-3 {
2005 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
2009 bias-disable;
2013 uart4_sleep_pins_d: uart4-sleep-3 {
2015 pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
2020 uart5_pins_a: uart5-0 {
2023 bias-disable;
2024 drive-push-pull;
2025 slew-rate = <0>;
2029 bias-disable;
2033 uart7_pins_a: uart7-0 {
2036 bias-disable;
2037 drive-push-pull;
2038 slew-rate = <0>;
2043 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
2044 bias-disable;
2048 uart7_pins_b: uart7-1 {
2051 bias-disable;
2052 drive-push-pull;
2053 slew-rate = <0>;
2057 bias-disable;
2061 uart7_pins_c: uart7-2 {
2064 bias-disable;
2065 drive-push-pull;
2066 slew-rate = <0>;
2070 bias-pull-up;
2074 uart7_idle_pins_c: uart7-idle-2 {
2080 bias-pull-up;
2084 uart7_sleep_pins_c: uart7-sleep-2 {
2091 uart8_pins_a: uart8-0 {
2093 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
2094 bias-disable;
2095 drive-push-pull;
2096 slew-rate = <0>;
2100 bias-disable;
2104 uart8_rtscts_pins_a: uart8rtscts-0 {
2108 bias-disable;
2112 usart2_pins_a: usart2-0 {
2115 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2116 bias-disable;
2117 drive-push-pull;
2118 slew-rate = <0>;
2121 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
2122 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
2123 bias-disable;
2127 usart2_sleep_pins_a: usart2-sleep-0 {
2130 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
2131 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
2132 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2136 usart2_pins_b: usart2-1 {
2139 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
2140 bias-disable;
2141 drive-push-pull;
2142 slew-rate = <0>;
2147 bias-disable;
2151 usart2_sleep_pins_b: usart2-sleep-1 {
2154 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
2160 usart2_pins_c: usart2-2 {
2162 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
2163 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2164 bias-disable;
2165 drive-push-pull;
2166 slew-rate = <3>;
2169 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
2170 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
2171 bias-disable;
2175 usart2_idle_pins_c: usart2-idle-2 {
2177 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
2178 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2181 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2182 bias-disable;
2183 drive-push-pull;
2184 slew-rate = <3>;
2187 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
2188 bias-disable;
2192 usart2_sleep_pins_c: usart2-sleep-2 {
2194 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
2195 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
2196 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
2197 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2201 usart3_pins_a: usart3-0 {
2204 bias-disable;
2205 drive-push-pull;
2206 slew-rate = <0>;
2210 bias-disable;
2214 usart3_pins_b: usart3-1 {
2218 bias-disable;
2219 drive-push-pull;
2220 slew-rate = <0>;
2225 bias-pull-up;
2229 usart3_idle_pins_b: usart3-idle-1 {
2236 bias-disable;
2237 drive-push-pull;
2238 slew-rate = <0>;
2242 bias-pull-up;
2246 usart3_sleep_pins_b: usart3-sleep-1 {
2255 usart3_pins_c: usart3-2 {
2259 bias-disable;
2260 drive-push-pull;
2261 slew-rate = <0>;
2266 bias-pull-up;
2270 usart3_idle_pins_c: usart3-idle-2 {
2277 bias-disable;
2278 drive-push-pull;
2279 slew-rate = <0>;
2283 bias-pull-up;
2287 usart3_sleep_pins_c: usart3-sleep-2 {
2296 usart3_pins_d: usart3-3 {
2300 bias-disable;
2301 drive-push-pull;
2302 slew-rate = <0>;
2305 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
2306 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2307 bias-disable;
2311 usart3_idle_pins_d: usart3-idle-3 {
2315 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
2318 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
2319 bias-disable;
2323 usart3_sleep_pins_d: usart3-sleep-3 {
2327 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
2328 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
2332 usart3_pins_e: usart3-4 {
2336 bias-disable;
2337 drive-push-pull;
2338 slew-rate = <0>;
2342 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2343 bias-pull-up;
2347 usart3_idle_pins_e: usart3-idle-4 {
2350 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
2354 bias-disable;
2355 drive-push-pull;
2356 slew-rate = <0>;
2360 bias-pull-up;
2364 usart3_sleep_pins_e: usart3-sleep-4 {
2368 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
2373 usbotg_hs_pins_a: usbotg-hs-0 {
2375 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
2379 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
2381 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
2382 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
2388 i2c2_pins_b2: i2c2-0 {
2391 bias-disable;
2392 drive-open-drain;
2393 slew-rate = <0>;
2397 i2c2_sleep_pins_b2: i2c2-sleep-0 {
2403 i2c4_pins_a: i2c4-0 {
2407 bias-disable;
2408 drive-open-drain;
2409 slew-rate = <0>;
2413 i2c4_sleep_pins_a: i2c4-sleep-0 {
2420 i2c6_pins_a: i2c6-0 {
2424 bias-disable;
2425 drive-open-drain;
2426 slew-rate = <0>;
2430 i2c6_sleep_pins_a: i2c6-sleep-0 {
2437 spi1_pins_a: spi1-0 {
2441 bias-disable;
2442 drive-push-pull;
2443 slew-rate = <1>;
2447 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
2448 bias-disable;
2452 spi1_pins_b: spi1-1 {
2454 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
2456 bias-disable;
2457 drive-push-pull;
2458 slew-rate = <1>;
2462 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
2463 bias-disable;