Lines Matching +full:stm32 +full:- +full:timers
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
78 timers2: timers@40000000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "st,stm32-timers";
84 clock-names = "int";
88 compatible = "st,stm32-pwm";
89 #pwm-cells = <3>;
94 compatible = "st,stm32-timer-trigger";
100 timers3: timers@40000400 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "st,stm32-timers";
106 clock-names = "int";
110 compatible = "st,stm32-pwm";
111 #pwm-cells = <3>;
116 compatible = "st,stm32-timer-trigger";
122 timers4: timers@40000800 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "st,stm32-timers";
128 clock-names = "int";
132 compatible = "st,stm32-pwm";
133 #pwm-cells = <3>;
138 compatible = "st,stm32-timer-trigger";
144 timers5: timers@40000c00 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "st,stm32-timers";
150 clock-names = "int";
154 compatible = "st,stm32-pwm";
155 #pwm-cells = <3>;
160 compatible = "st,stm32-timer-trigger";
166 timers6: timers@40001000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "st,stm32-timers";
172 clock-names = "int";
176 compatible = "st,stm32-timer-trigger";
182 timers7: timers@40001400 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "st,stm32-timers";
188 clock-names = "int";
192 compatible = "st,stm32-timer-trigger";
198 timers12: timers@40001800 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "st,stm32-timers";
204 clock-names = "int";
208 compatible = "st,stm32-pwm";
209 #pwm-cells = <3>;
214 compatible = "st,stm32-timer-trigger";
220 timers13: timers@40001c00 {
221 compatible = "st,stm32-timers";
224 clock-names = "int";
228 compatible = "st,stm32-pwm";
229 #pwm-cells = <3>;
234 timers14: timers@40002000 {
235 compatible = "st,stm32-timers";
238 clock-names = "int";
242 compatible = "st,stm32-pwm";
243 #pwm-cells = <3>;
249 compatible = "st,stm32-rtc";
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
254 interrupt-parent = <&exti>;
261 compatible = "st,stm32f7-uart";
269 compatible = "st,stm32f7-uart";
277 compatible = "st,stm32f7-uart";
285 compatible = "st,stm32f7-uart";
293 compatible = "st,stm32f7-i2c";
299 #address-cells = <1>;
300 #size-cells = <0>;
305 compatible = "st,stm32f7-i2c";
311 #address-cells = <1>;
312 #size-cells = <0>;
317 compatible = "st,stm32f7-i2c";
323 #address-cells = <1>;
324 #size-cells = <0>;
329 compatible = "st,stm32f7-i2c";
335 #address-cells = <1>;
336 #size-cells = <0>;
341 compatible = "st,stm32-cec";
345 clock-names = "cec", "hdmi-cec";
350 compatible = "st,stm32f7-uart";
358 compatible = "st,stm32f7-uart";
365 timers1: timers@40010000 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 compatible = "st,stm32-timers";
371 clock-names = "int";
375 compatible = "st,stm32-pwm";
376 #pwm-cells = <3>;
381 compatible = "st,stm32-timer-trigger";
387 timers8: timers@40010400 {
388 #address-cells = <1>;
389 #size-cells = <0>;
390 compatible = "st,stm32-timers";
393 clock-names = "int";
397 compatible = "st,stm32-pwm";
398 #pwm-cells = <3>;
403 compatible = "st,stm32-timer-trigger";
410 compatible = "st,stm32f7-uart";
418 compatible = "st,stm32f7-uart";
427 arm,primecell-periphid = <0x00880180>;
430 clock-names = "apb_pclk";
432 max-frequency = <48000000>;
438 arm,primecell-periphid = <0x00880180>;
441 clock-names = "apb_pclk";
443 max-frequency = <48000000>;
448 compatible = "st,stm32-syscfg", "syscon";
452 exti: interrupt-controller@40013c00 {
453 compatible = "st,stm32-exti";
454 interrupt-controller;
455 #interrupt-cells = <2>;
460 timers9: timers@40014000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "st,stm32-timers";
466 clock-names = "int";
470 compatible = "st,stm32-pwm";
471 #pwm-cells = <3>;
476 compatible = "st,stm32-timer-trigger";
482 timers10: timers@40014400 {
483 compatible = "st,stm32-timers";
486 clock-names = "int";
490 compatible = "st,stm32-pwm";
491 #pwm-cells = <3>;
496 timers11: timers@40014800 {
497 compatible = "st,stm32-timers";
500 clock-names = "int";
504 compatible = "st,stm32-pwm";
505 #pwm-cells = <3>;
510 pwrcfg: power-config@40007000 {
511 compatible = "st,stm32-power-config", "syscon";
516 compatible = "st,stm32f7-crc";
523 #reset-cells = <1>;
524 #clock-cells = <2>;
525 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
529 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
530 assigned-clock-rates = <1000000>;
533 dma1: dma-controller@40026000 {
534 compatible = "st,stm32-dma";
545 #dma-cells = <4>;
549 dma2: dma-controller@40026400 {
550 compatible = "st,stm32-dma";
561 #dma-cells = <4>;
567 compatible = "st,stm32f7-hsotg";
571 clock-names = "otg";
572 g-rx-fifo-size = <256>;
573 g-np-tx-fifo-size = <32>;
574 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
579 compatible = "st,stm32f4x9-fsotg";
583 clock-names = "otg";